Patents by Inventor Yuan Liang

Yuan Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7211894
    Abstract: According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, a dielectric disposed between the first conductive plane and the second conductive plane, a third conductive plane electrically coupled to the second terminal and not electrically coupled to the first terminal, and a second dielectric disposed between the second conductive plane and the third conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: May 1, 2007
    Assignee: Intel Corporation
    Inventors: Jennifer A. Hester, Yuan-Liang Li, Michael M. Desmith, David G. Figueroa, Dong Zhong
  • Patent number: 7205638
    Abstract: An improved silicon building block is disclosed. In an embodiment, the silicon building block has at least two vias through it. The silicon building block is doped and the vias filled with a first material, and, optionally, selected ones of the vias filled instead with a second material. In an alternative embodiment, regions of the silicon building block have metal deposited on them.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: April 17, 2007
    Assignee: Intel Corporation
    Inventors: David Gregory Figueroa, Dong Zhong, Yuan-Liang Li, Jiangqi He, Cengiz Ahmet Palanduz
  • Publication number: 20070080101
    Abstract: An isotonic Ozone generator is disclosed. A supplementary liquid reservoir with pipeline is connected to the outlet of water-gas mixer with 3-way adapter and a flow meter pump at lower position. The hypertonic solution is accommodated in the liquid reservoir. With precise control of flow meter pump, the hypertonic solution from liquid reservoir is mixing with concentrated Ozone water from water-gas mixer at constant rate and ratio to form ISOTONIC OZONE WATER for directly applying onto internal or external wounds of human bodies for disinfection.
    Type: Application
    Filed: October 11, 2005
    Publication date: April 12, 2007
    Inventor: Yuan-Liang Huang
  • Patent number: 7176565
    Abstract: A multilayer capacitor comprises separate terminals on at least three sides, and on as many as six sides. The capacitor can be fabricated in a large number of different configurations, types, and sizes, depending upon the target application. The separate terminals that are disposed on different sides of the capacitor can be readily coupled to a variety of different adjacent conductors, such as die terminals (including bumpless terminals or bars), IC package terminals (including pads or bars), and the terminals of adjacent discrete components. Methods of fabrication, as well as application of the capacitor to an electronic assembly, are also described.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventors: Yuan-Liang Li, David G. Figueroa, Chee-Yee Chung
  • Patent number: 7173803
    Abstract: An inter-digital capacitor may be used in a power socket for a microelectronic device. In one embodiment an integrated, low-resistance power and ground terminal configuration is disclosed. The capacitor plates are alternatively coupled to the power and ground terminals. Two polarity types are disclosed. A method of operation is also described.
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: February 6, 2007
    Assignee: Intel Corporation
    Inventors: Dong Zhong, Jiangqi He, Yuan-Liang Li
  • Publication number: 20070002519
    Abstract: In some embodiments, a capacitor includes a first conductive layer electrically coupled to a first terminal, a second conductive layer electrically coupled to a second terminal, a floated conductive layer disposed between the first and second conductive layers, and a plurality of non-conductive layers respectively disposed between each of the conductive layers. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Yuan-Liang Li, David Figueroa, Nicholas Holmberg
  • Patent number: 7145239
    Abstract: Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: December 5, 2006
    Assignee: Intel Corporation
    Inventors: Yuan-Liang Li, Jiangqi He, Dong Zhong, David G. Figueroa
  • Publication number: 20060267216
    Abstract: A series of plated through hole (PTH) vias are interconnected by traces that alternate between a top surface and a bottom surface of a dielectric board. The PTH vias in the series can be positioned to create a collinear inductive filter, a coil-type inductive filter, or a transformer. Multiple, electrically isolated series of interconnected PTH vias can be used as a multi-phase inductive filter in one embodiment. In another embodiment, multiple series of interconnected PTH vias are electrically connected by a linking portion of conductive material, resulting in a low-resistance inductive filter. Ferromagnetic material patterns can be embedded in the dielectric board to enhance the inductive characteristics of the interconnected via structures. In one embodiment, a closed-end pattern is provided with two series of interconnected vias coiling around the pattern, resulting in an embedded transformer structure.
    Type: Application
    Filed: August 4, 2006
    Publication date: November 30, 2006
    Inventors: Yuan-Liang Li, David Figueroa
  • Publication number: 20060261465
    Abstract: Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.
    Type: Application
    Filed: July 26, 2006
    Publication date: November 23, 2006
    Inventors: Yuan-Liang Li, Jiangqi He, Dong Zhong, David Figueroa
  • Publication number: 20060256502
    Abstract: A multilayer capacitor comprises separate terminals on at least three sides, and on as many as six sides. The capacitor can be fabricated in a large number of different configurations, types, and sizes, depending upon the target application. The separate terminals that are disposed on different sides of the capacitor can be readily coupled to a variety of different adjacent conductors, such as die terminals (including bumpless terminals or bars), IC package terminals (including pads or bars), and the terminals of adjacent discrete components. Methods of fabrication, as well as application of the capacitor to an electronic assembly, are also described.
    Type: Application
    Filed: July 27, 2006
    Publication date: November 16, 2006
    Inventors: Yuan-Liang Li, David Figueroa, Chee-Yee Chung
  • Patent number: 7136272
    Abstract: A capacitor has at least one plate of a first polarity and at least two plates of a second polarity, with a terminal electrically connected to the at least two plates of the second polarity such that the electrical plate connections are remote from an edge of the connected plates.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: November 14, 2006
    Assignee: Intel Corporation
    Inventors: Yuan-Liang Li, Jiangqi He, Dong Zhong
  • Patent number: 7133294
    Abstract: To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: November 7, 2006
    Assignee: Intel Corporation
    Inventors: Priyavadan R. Patel, Chee-Yee Chung, David G. Figueroa, Robert L. Sankman, Yuan-Liang Li, Hong Xie, William P. Pinello
  • Patent number: 7111271
    Abstract: A series of plated through hole (PTH) vias are interconnected by traces that alternate between a top surface and a bottom surface of a dielectric board. The PTH vias in the series can be positioned to create a collinear inductive filter, a coil-type inductive filter, or a transformer. Multiple, electrically isolated series of interconnected PTH vias can be used as a multi-phase inductive filter in one embodiment. In another embodiment, multiple series of interconnected PTH vias are electrically connected by a linking portion of conductive material, resulting in a low-resistance inductive filter. Ferromagnetic material patterns can be embedded in the dielectric board to enhance the inductive characteristics of the interconnected via structures. In one embodiment, a closed-end pattern is provided with two series of interconnected vias coiling around the pattern, resulting in an embedded transformer structure.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: September 19, 2006
    Assignee: Intel Corporation
    Inventors: Yuan-Liang Li, David G. Figueroa
  • Publication number: 20060197726
    Abstract: A display device has a pixel array substrate that contains a support substrate and a plurality of pixel areas arranged on the support substrate. Each pixel area contains a pixel electrode and a capacitor electrode. Scan lines and common lines are also provided, where each common line has portions provided in respective pixel areas. Each pixel area has a storage capacitance defined by an overlapping area between a respective capacitor electrode and a respective one of a scan line and common line, where the storage capacitances of pixel areas along each scan line varies along the scan line.
    Type: Application
    Filed: March 1, 2006
    Publication date: September 7, 2006
    Inventor: Yuan-Liang Wu
  • Publication number: 20060139847
    Abstract: According to some embodiments, a capacitor includes a first external capacitor plane comprising a first at least one terminal of a first polarity, and a first internal capacitor plane comprising a second at least one terminal of the first polarity. The second at least one terminal of the first polarity may be electrically coupled to the first at least one terminal of the first polarity, and a total area of the second at least one terminal of the first polarity may be less than a total area of the first at least one terminal of the first polarity.
    Type: Application
    Filed: December 28, 2004
    Publication date: June 29, 2006
    Inventors: Yuan-Liang Li, David Figueroa, Farzaneh Yahyaei-moayyed, Dong Zhong
  • Publication number: 20060138639
    Abstract: According to some embodiments, an apparatus includes a first conductive pad, a first conductive plane, first dielectric material disposed between the first conductive plane and the first conductive pad, a second conductive plane, second dielectric material disposed between the first conductive plane and the second conductive plane, and a first conductive network.
    Type: Application
    Filed: December 28, 2004
    Publication date: June 29, 2006
    Inventors: David Figueroa, Jennifer Hester, Yuan-Liang Li
  • Patent number: 7063569
    Abstract: A socket and fabrication method provide enhanced performance. The socket includes a base, and a plurality of signal contacts disposed within the base. A grounding fence is also disposed within the base such that the grounding fence laterally isolates the signal contacts from one another. The use of a grounding fence therefore enables elimination or significant reduction of ground contacts and therefore provides more signaling opportunities for a given amount of real estate.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: June 20, 2006
    Assignee: Intel Corporation
    Inventors: David G. Figueroa, Yuan-Liang Li
  • Patent number: 7058102
    Abstract: A device for producing laser radiation, the device comprising: an elongate sample of a quasi-three-level laser material; a source of pumping radiation; and a concentrator configured such that at least some of the pumping radiation emitted by the source of pumping radiation is concentrated by the concentrator and subsequently enters the sample through a side surface thereof.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: June 6, 2006
    Assignee: DSO National Laboratories
    Inventors: Poh Boon Phua, Kin Seng Lai, Rui Fen Wu, Yuan Liang Lim, Wei Pin Ernest Lau
  • Publication number: 20060091564
    Abstract: According to some embodiments, a system includes an integrated circuit package to support an integrated circuit die. The integrated circuit package may include a plurality of conductive contacts and a decoupling capacitor. The decoupling capacitor may include a positive terminal contact pad coupled to a first one of the plurality of conductive contacts, the positive terminal contact pad comprising a first substantially non-conductive area, and a negative terminal contact pad coupled to a second one of the plurality of conductive contacts, the negative terminal contact pad comprising a second substantially non-conductive area.
    Type: Application
    Filed: October 29, 2004
    Publication date: May 4, 2006
    Inventors: Dong Zhong, David Figueroa, Yuan-Liang Li, Michael Desmith
  • Publication number: 20060087012
    Abstract: According to some embodiments, a system includes an integrated circuit package to support an integrated circuit die. The integrated circuit package may include a plurality of conductive contacts, and an element having a plurality of resistive portions, each of the plurality of resistive portions being coupled to a respective one of the plurality of conductive contacts. The integrated circuit package may further include a decoupling capacitor having a plurality of capacitor pads, each of the plurality of capacitor pads being coupled to a respective one of the plurality of resistive portions.
    Type: Application
    Filed: October 21, 2004
    Publication date: April 27, 2006
    Inventors: Dong Zhong, David Figneroa, Yuan-Liang Li