Abstract: A computer processing system is provided for enhancing video-based language learning. The system includes a video server for storing videos that use one or more languages to be learned. The system further includes a video metadata database for storing translations of sentences uttered in the videos, character profiles of characters appearing in the videos, and mappings between the sentences and a learner profile. The system also includes a learner profile database for storing learner profiles. The system additionally includes a semantic analyzer and matching engine for finding, for at least a given video and a given learner, alternative sentences for and responsive to the translations of the sentences uttered in the given video that conflict with a respective learner profile for the given learner. The computer processing system further includes a presentation system for playing back the given video and providing the alternative sentences to the given learner.

Abstract: A resin composition includes 100 parts by weight of hydrocarbon resin polymers and 0.01 to 50 parts by weight of divinyl aromatic compound. A substrate structure includes a resin layer and a conductive layer disposed on the resin layer, wherein the resin layer is formed from the resin composition. A manufacturing method of the resin composition includes the following steps: providing a mixture, wherein the mixture includes a monovinyl aromatic compound and a divinyl aromatic compound, and optionally includes a bridged ring compound; polymerizing the mixture to form a crude composition; and purifying the crude composition to prepare the resin composition.

Abstract: A negative electrode plate includes a negative electrode active material layer. The negative electrode active material layer includes a negative electrode active substance and lithium-philic nanoparticles capable of alloying with lithium. A secondary battery includes a positive electrode plate, the negative electrode plate, and a separator provided between the positive electrode plate and the negative electrode plate.

Abstract: A two-dimensional electronic component includes a substrate; an artificial two-dimensional (2D) material disposed on the substrate; and a first metallic electrode disposed on the artificial 2D material. The artificial 2D material includes a layered atomic structure including a middle atomic layer, a lower atomic layer disposed on a lower surface of the middle atomic layer, and an upper atomic layer disposed on an upper surface of the middle atomic layer respectively. The upper atomic layer and the first metallic electrode are attracted together at a junction therebetween by metallic bonding.

Abstract: In some embodiments, the present disclosure relates to a method in which a first set of one or more voltage pulses is applied to a piezoelectric device over a first time period. During the first time period, the method determines whether a performance parameter of the piezoelectric device has a first value that deviates from a reference value by more than a predetermined value. Based on whether the first value deviates from the reference value by more than the predetermined value, the method selectively applies a second set of one or more voltage pulses to the piezoelectric device over a second time period. The second time period is after the first time period and the second set of one or more voltage pulses differs in magnitude and/or polarity from the first set of one or more voltage pulses.

Abstract: A resin, including a compound having the following Formula 1-1: wherein n ranges from 1 to 5, and R1, R2, R3 and R4 are as defined herein.

Abstract: A benzoxazine resin, including a compound of the following Formula 1-1: where R1, R2, and R3 are as defined herein.

Abstract: A phase shifter includes a first transistor and a second transistor. The first transistor includes a first gate terminal configured to receive a first voltage. The first transistor is configured to adjust at least a resistance or a first capacitance of the phase shifter responsive to the first voltage. The second transistor is coupled to the first transistor. The second transistor includes a second gate terminal configured to receive a second voltage. The second transistor is configured to adjust a second capacitance of the phase shifter responsive to the second voltage. The second gate terminal includes a first polysilicon portion and a second polysilicon portion extending in a first direction. The first polysilicon portion and the second polysilicon portion are positioned along opposite edges of an active region of the first transistor and the second transistor.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: An FAP/CD40 binding molecule and the medicinal use thereof. Specifically, provided are an FAP binding molecule, a CD40 binding molecule and an FAP/CD40 binding molecule, a method for preventing and treating diseases (such as tumors or cancers) using same, and the medicinal use thereof.

Abstract: A semiconductor structure includes an interconnect structure, a passivation structure, a first capacitor, and a contact feature. The interconnect structure is disposed over a semiconductor substrate. The passivation structure is disposed over the interconnect structure. The first capacitor is disposed within the passivation structure. The contact feature is disposed over the passivation structure, wherein the first capacitor is proximal to a corner of the contact feature. A method of manufacturing the semiconductor structure is also provided.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure that includes a metal-insulator-metal (MIM) device disposed over a substrate. The MIM device includes a first electrode and a second electrode stacked over the substrate. A dielectric layer is arranged between the first electrode and the second electrode. A getter layer is disposed over the substrate and is separated from the dielectric layer by the first electrode. The MIM device includes a middle portion having a first non-zero concentration of hydrogen and a peripheral portion having both a second non-zero concentration of hydrogen that is greater than the first non-zero concentration and a third non-zero concentration of hydrogen that is less than the first non-zero concentration. The middle portion includes the dielectric layer and the peripheral portion includes the getter layer.

Abstract: An artificial double-layer two-dimensional material includes a first layered atomic structure and a second layered atomic structure. The first layered atomic structure includes a first middle atomic layer, a first lower atomic layer, and a first upper atomic layer. The first lower and the first upper atomic layers are disposed on lower and upper surfaces of the first middle atomic layer respectively. The second layered atomic structure includes a second middle atomic layer, a second lower atomic layer, and a second upper atomic layer. The second lower and the second upper atomic layers are disposed on lower and upper surfaces of the second middle atomic layer respectively. The first middle atomic layer and the second middle atomic layer are two-dimensional planar atomic structures formed of transition metals. The first lower and the first upper atomic layers are 2D planar atomic structures formed of heterogeneous atom.

Abstract: A semiconductor structure includes a source/drain feature in the semiconductor layer. The semiconductor structure includes a dielectric layer over the source/drain feature. The semiconductor structure includes a silicide layer over the source/drain feature. The semiconductor structure includes a barrier layer over the silicide layer. The semiconductor structure includes a seed layer over the barrier layer. The semiconductor structure includes a metal layer between a sidewall of the seed layer and a sidewall of the dielectric layer, a sidewall of each of the silicide layer, the barrier layer, and the metal layer directly contacting the sidewall of the dielectric layer. The semiconductor structure includes a source/drain contact over the seed layer.

Abstract: A driving mechanism is provided for moving an optical element, including a fixed module, a movable module holding the optical element, a driving assembly for driving the movable module to move relative to the fixed module, a position-sensing element, and a 3D circuit. The fixed module has a base, and the position-sensing element is disposed on the base to detect the movement of the movable module relative to the fixed module. The 3D circuit is embedded in the base and electrically connected to the position-sensing element.

Abstract: A multi-layer display module includes a first display panel, and a second display panel. The second display panel is located on one side of the first display panel and overlapped with the first display panel. There is a space between the first display panel and the second display panel. Transmittance of the second display panel is T2, luminance of the first display panel is L1, and luminance of the second display panel is L2. The multi-layer display module complies with T ? 2 > 40 ? % and 0.8 ? L ? 1 L ? 2 * ( 1 - T ? 2 ) .

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a buffer layer on the substrate, forming a mesa isolation on the HEMT region, forming a HEMT on the mesa isolation, and then forming a capacitor on the capacitor region. Preferably, a bottom electrode of the capacitor contacts the buffer layer directly.

Abstract: A voltage-controlled oscillator (VCO) includes a power supply source, a voltage source, a reference voltage node, first and second transistors, each including a source terminal coupled to the reference voltage node, and first through fourth conductive structures. The first conductive structure includes a first terminal coupled to the power supply source, a first extending portion coupled between the first terminal and a drain terminal of the first transistor, and a second extending portion coupled between the first terminal and a drain terminal of the second transistor, and the second conductive structure includes a second terminal coupled to the voltage source, a third extending portion coupled in series with the third conductive structure between the second terminal and a gate of the first transistor, and a fourth extending portion coupled in series with the fourth conductive structure between the second terminal and a gate of the second transistor.

Abstract: A semiconductor device with a deep trench isolation and a shallow trench isolation includes a substrate. The substrate is divided into a high voltage transistor region and a low voltage transistor region. A deep trench is disposed within the high voltage transistor region. The deep trench includes a first trench and a second trench. The first trench includes a first bottom. The second trench extends from the first bottom toward a bottom of the substrate. A first shallow trench and a second shallow trench are disposed within the low voltage transistor region. A length of the first shallow trench is the same as a length of the second trench. An insulating layer fills in the first trench, the second trench, the first shallow trench and the second shallow trench.

Abstract: A semiconductor device includes a substrate including a well region of a first conductive type; a first gate electrode on the substrate; a second gate electrode on the substrate; a first doped region embedded within the well region and is of the first conductive type, a second doped region embedded within the well region and is of the first conductive type, and a third doped region embedded within the well region and is of the first conductive type; and a first interconnection structure electrically connecting the first gate electrode and the second gate electrode. The first doped region and the second doped region are on opposite sides of the first gate electrode.