Patents by Inventor Yuan Lo

Yuan Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory cell with high endurance for multiple program operations
    Patent number: 9792993
    Abstract: A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating gate. The common floating gate is coupled to the second floating gate transistor and the first floating gate transistor. The memory cell is programmed and erased through the common floating gate on the second floating gate transistor, and is read through the first floating gate transistor and the read transistor.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: October 17, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching
  • MEMORY CELL WITH HIGH ENDURANCE FOR MULTIPLE PROGRAM OPERATIONS
    Publication number: 20170206969
    Abstract: A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating gate. The common floating gate is coupled to the second floating gate transistor and the first floating gate transistor. The memory cell is programmed and erased through the common floating gate on the second floating gate transistor, and is read through the first floating gate transistor and the read transistor.
    Type: Application
    Filed: January 16, 2017
    Publication date: July 20, 2017
    Inventors: Chun-Yuan Lo, Shih-Chen Wang, Wen-Hao Ching
  • MOBILE DEVICE
    Publication number: 20170155198
    Abstract: A mobile device includes a metal back cover and a printed circuit board. The metal back cover has a slot. The printed circuit board includes a dielectric substrate, a first metal element, a second metal element, and via elements. The first metal element is disposed on a top surface of the dielectric substrate. The second metal element is disposed on a bottom surface of the dielectric substrate. The via elements are formed in the dielectric substrate, and are coupled between the first metal element and the second metal element. The first metal element is coupled to the metal back cover, such that a slot antenna is formed by the printed circuit board and the slot of the metal back cover. The slot antenna is excited by a signal source which is coupled to the second metal element.
    Type: Application
    Filed: December 31, 2015
    Publication date: June 1, 2017
    Inventors: Wen-Yuan LO, Jui-Chun JAO, Lieh-Hung LIAO
  • Color filter substrate and display device
    Patent number: 9664826
    Abstract: A color filter substrate includes a transparent substrate and a plurality of color filter patterns. The transparent substrate has an upper surface and a lower surface opposite to each other, and a plurality of containing cavities. The containing cavities extend from the upper surface toward the lower surface and separate from each other. Each containing cavity has a bottom surface. The color filter patterns are disposed on the transparent substrate and located inside the containing cavities, respectively. The color filter patterns contact with the corresponding bottom surfaces, respectively.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: May 30, 2017
    Assignee: E Ink Holdings Inc.
    Inventors: Tai-Yuan Lee, Po-Yuan Lo
  • Memory cell with different program and read paths for achieving high endurance
    Patent number: 9653173
    Abstract: A memory cell includes a coupling device, a read transistor, a first read selection transistor, a second read selection transistor, an erase device, a program transistor, and a program selection transistor. The coupling device is formed on a first doped region. The erase device is formed on a second doped region. The read transistor, the first read selection transistor, the second read selection transistor, the program transistor, and the program selection transistor are formed on a third doped region. A gate terminal of the coupling device is coupled to a common floating gate. A gate terminal of the erase device is coupled to the floating gate. During a program operation, electrical charges are moved from the common floating gate. During an erase operation, electrical charges are ejected from the common floating gate to the erase device.
    Type: Grant
    Filed: December 4, 2016
    Date of Patent: May 16, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Chun-Yuan Lo, Wei-Chen Chang, Shih-Chen Wang
  • Mobile device
    Patent number: 9601825
    Abstract: A mobile device includes a ground element, a first antenna, a second antenna, and a filter. The filter is disposed between the first antenna and the second antenna. The filter includes a main branch and a tuning branch. The tuning branch is coupled through the main branch to the ground element. The first antenna and the second antenna cover the same operation frequency band. The filter is configured to enhance the isolation between the first antenna and the second antenna in the operation frequency band.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: March 21, 2017
    Assignee: QUANTA COMPUTER INC.
    Inventor: Wen-Yuan Lo
  • REFLECTIVE DISPLAY DEVICE
    Publication number: 20170031227
    Abstract: A reflective display device includes an electrophoretic display module, an adhesive layer, and a color filter layer. The adhesive layer is located on the electrophoretic display module. The color filter layer is located on the adhesive layer, and the adhesive layer is between the electrophoretic display module and the color filter layer. The color filter layer includes at least one color resist.
    Type: Application
    Filed: May 2, 2016
    Publication date: February 2, 2017
    Inventors: Po-Yuan LO, Tai-Yuan LEE, Hsiao-Tung CHU
  • USER EQUIPMENT, MOBILE HOTSPOT EQUIPMENT, BACKHAUL DEVICE AND METHOD FOR ESTABLISHING A PATH LOSS MODEL DATABASE
    Publication number: 20160337892
    Abstract: A user equipment (UE), a mobile hotspot equipment, a backhaul device and a method for establishing a path loss model database are provided. The UE receives a wireless signal from a first surrounding mobile hotspot equipment, and measures the wireless signal during a time interval so as to generate received signal information corresponding to the wireless signal. Thereafter, the UE transmits a measurement response message that includes an identity of the first surrounding mobile hotspot equipment and the received signal information to the backhaul device via the mobile hotspot equipment. Accordingly, the backhaul device establishes a path loss model according to the received signal information and stores the path loss model into a path loss model database.
    Type: Application
    Filed: December 3, 2015
    Publication date: November 17, 2016
    Inventors: Chih-Yuan LO, Yang-Han LEE, Yi-Hsueh TSAI, Yi-Ting LIN
  • Control method of resistive random-access memory
    Patent number: 9484094
    Abstract: A control method of a resistive random-access memory is provided. Firstly, an action is performed on the resistive random-access memory, so that the resistive random-access memory has a specified state. Then, an operation period begins. During a first sub-period of the operation period, a first control signal with a first polarity is provided. During a second sub-period of the operation period, a second control signal with a second polarity is provided. During a third sub-period of the operation period, a third control signal with the first polarity is provided. During a fourth sub-period of the operation period, a read signal is provided, so that the resistive random-access memory generates a read current. According to the read current, a controlling circuit verifies whether the resistive random-access memory is in the specified state.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: November 1, 2016
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chia-Jung Hsu, Wein-Town Sun, Chun-Yuan Lo
  • DISPLAY PANEL
    Publication number: 20160291438
    Abstract: A display panel includes a flexible substrate, a first conductive layer, an insulating layer, a second conductive layer and a display layer. The flexible substrate includes a central area and at least one peripheral area. The first conductive layer is disposed on the flexible substrate. The insulating layer is disposed on the first conductive layer. The insulating layer includes a central insulating portion and at least one peripheral insulating portion. The peripheral insulating portion is located above the peripheral area. The central insulating portion is located above the central area. The peripheral insulating portion is more flexible than the central insulating portion. The second conductive layer is disposed on the insulating layer, and the insulating layer separates the first conductive layer from the second conductive layer. The display layer is disposed on the second conductive layer.
    Type: Application
    Filed: December 18, 2015
    Publication date: October 6, 2016
    Inventors: Po-Yuan LO, Lee-Tyng CHEN
  • Non-volatile memory apparatus and erasing method thereof
    Patent number: 9424939
    Abstract: The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: August 23, 2016
    Assignee: eMemory Technology Inc.
    Inventors: Yu-Hsiung Tsai, Chun-Yuan Lo
  • LIQUID CRYSTAL COMPOUND AND LIQUID CRYSTAL COMPOSITION EMPLOYING THE SAME
    Publication number: 20160222295
    Abstract: A liquid crystal compound and a composition employing the same are provided. The liquid crystal compound has a structure represented by Formula (I) wherein R1, A1, A2, A3, A4, Z1, Z2, Z3, Z4, X, m, n, o, and p are defined as in the description.
    Type: Application
    Filed: January 27, 2016
    Publication date: August 4, 2016
    Inventors: CHIH-YUAN LO, HSIN-CHENG LIU, GUO-YU LAN, CHUN-CHIH WANG
  • High-K metal gate process for lowering junction leakage and interface traps in NMOS transistor
    Patent number: 9406516
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: August 2, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jian-Cun Ke, Chih-Wei Yang, Kun-Yuan Lo, Chia-Fu Hsu, Shao-Wei Wang
  • CONTROL METHOD OF RESISTIVE RANDOM-ACCESS MEMORY
    Publication number: 20160211020
    Abstract: A control method of a resistive random-access memory is provided. Firstly, an action is performed on the resistive random-access memory, so that the resistive random-access memory has a specified state. Then, an operation period begins. During a first sub-period of the operation period, a first control signal with a first polarity is provided. During a second sub-period of the operation period, a second control signal with a second polarity is provided. During a third sub-period of the operation period, a third control signal with the first polarity is provided. During a fourth sub-period of the operation period, a read signal is provided, so that the resistive random-access memory generates a read current. According to the read current, a controlling circuit verifies whether the resistive random-access memory is in the specified state.
    Type: Application
    Filed: October 1, 2015
    Publication date: July 21, 2016
    Inventors: Chia-Jung Hsu, Wein-Town Sun, Chun-Yuan Lo
  • REFLECTIVE DISPLAY DEVICE
    Publication number: 20160170281
    Abstract: A reflective display device includes an electrophoretic display (EPD) module, a supporting member, a first anti-reflective layer, and a color filter (CFA) layer. The EPD module includes an array substrate, a protective layer, and an electronic ink (e-ink) layer. The e-ink layer is between the array substrate and the protective layer. The supporting member has a first surface and a second surface opposite to the first surface. The first anti-reflective layer is located on the first surface of the supporting member and in contact with the supporting member. The thickness of the first anti-reflective layer is ¼ wavelength of a visible light. The CFA layer is between the protective layer and the second surface of the supporting member.
    Type: Application
    Filed: August 13, 2015
    Publication date: June 16, 2016
    Inventors: Po-Yuan LO, Wei-Chen TSAI
  • MEMORY CELL ARRAY OF RESISTIVE RANDOM-ACCESS MEMORIES
    Publication number: 20160148686
    Abstract: A memory cell array includes a first bit line, a first word line, a first source line pair and a first memory cell. A select terminal of the first memory cell is connected with the first word line. A first control terminal of the first memory cell is connected with a first source line of the first source line pair. A second control terminal of the first memory cell is connected with a second source line of the first source line pair. A third control terminal of the first memory cell is connected with the first bit line.
    Type: Application
    Filed: October 7, 2015
    Publication date: May 26, 2016
    Inventors: Chia-Jung Hsu, Wein-Town Sun, Ching-Sung Yang, Chi-Yi Shao, Chun-Yuan Lo, Yu-Hsiung Tsai, Ching-Yuan Lin
  • Display device and fabrication method of display device
    Patent number: 9316885
    Abstract: A display device including a first substrate, a second substrate, a display layer, a color filter layer, a transparent electrode layer and a transparent sealing is provided. The first substrate is opposite to the second substrate. The display layer is disposed between the first substrate and the second substrate. The color filter layer is disposed between the display layer and the first substrate. The transparent electrode layer is disposed between the color filter layer and the display layer. The transparent sealing surrounds the display layer so that the display layer is sealed between the first substrate and the second substrate, wherein a curable temperature of the transparent sealing is lower than or equal to 40° C. A fabrication method of a display device is further provided herein.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: April 19, 2016
    Assignee: E Ink Holdings Inc.
    Inventors: Po-Yuan Lo, Tai-Yuan Lee
  • Field-effect transistor and fabricating method thereof
    Patent number: 9312352
    Abstract: A method for fabricating a field-effect transistor is provided. The method includes: forming a gate dielectric layer and a barrier layer on a substrate in sequence; forming a first silicon layer on and in contact with the barrier layer; performing a thermal treatment to form a silicide layer between the barrier layer and the first silicon layer; and forming a second silicon layer on and in contact with the first silicon layer.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: April 12, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kun-Yuan Lo, Chih-Wei Yang, Cheng-Guo Chen, Rai-Min Huang, Jian-Cun Ke
  • NON-VOLATILE MEMORY APPARATUS AND ERASING METHOD THEREOF
    Publication number: 20160042795
    Abstract: The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.
    Type: Application
    Filed: October 23, 2015
    Publication date: February 11, 2016
    Inventors: Yu-Hsiung Tsai, Chun-Yuan Lo
  • FIELD-EFFECT TRANSISTOR AND FABRICATING METHOD THEREOF
    Publication number: 20160027885
    Abstract: A method for fabricating a field-effect transistor is provided. The method includes: forming a gate dielectric layer and a barrier layer on a substrate in sequence; forming a first silicon layer on and in contact with the barrier layer; performing a thermal treatment to form a silicide layer between the barrier layer and the first silicon layer; and forming a second silicon layer on and in contact with the first silicon layer.
    Type: Application
    Filed: October 2, 2015
    Publication date: January 28, 2016
    Inventors: Kun-Yuan LO, Chih-Wei YANG, Cheng-Guo CHEN, Rai-Min HUANG, Jian-Cun KE