Abstract: A Ball Grid Array (BGA) formed on printed circuit board is provided. The BGA comprises a first solder ball module and a second solder ball module. The first solder ball module comprises a plurality of first solder balls, wherein one of the first solder balls is grounded for shielding two other first solder balls, and one of the first solder balls is floating. The second solder ball module comprises a plurality of second solder balls, wherein two of the second solder balls are grounded and one of the two grounded second solder balls penetrates the printed circuit board through a plated through hole formed on the printed circuit board for shielding two first solder balls among the first solder balls.

Abstract: The invention provides a non-volatile memory apparatus and an erasing method thereof. The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.

Abstract: A field-effect transistor comprises a substrate, a gate dielectric layer, a barrier layer, a metal gate electrode and a source/drain structure. The gate dielectric layer is disposed on the substrate. The barrier layer having a titanium-rich surface is disposed on the gate dielectric layer. The metal gate electrode is disposed on the titanium-diffused surface. The source/drain structure is formed in the substrate and adjacent to the metal gate electrode.

Abstract: An electrophoretic display apparatus includes a first substrate, a plurality of sub-pixel structures, a color filter array, and an electrophoretic layer. The sub-pixel structures are disposed on the first substrate, and each of the sub-pixel structures includes a plurality of sub-pixel sub-structures. The color filter array is disposed above the sub-pixel structures, and includes a plurality of filter units. The filter units are divided into a plurality of groups having different colors, and the filter units belonging to the groups having different colors are alternately disposed above the sub-pixel structures. Each of the filter units corresponds to the sub-pixel sub-structures of at least one sub-pixel structure, and at least two of the sub-pixel sub-structures of the same sub-pixel structure are adapted to be applied different voltages. The electrophoretic layer is disposed on the sub-pixel structures.

Abstract: A pixel array includes a substrate and color filter patterns. The substrate has pixel areas. Each of the pixel areas has a first sub-pixel region, a second sub-pixel region, a third sub-pixel region and a fourth sub-pixel region. The first, the second, the third and the fourth sub-pixel regions are arranged sequentially in the clockwise direction. The color filter patterns are disposed on the pixel areas of the substrate and located in the first, the second, the third and the fourth sub-pixel regions. The color filter patterns located in the first, the second, the third and the fourth sub-pixel regions of each of the pixel areas respectively have different colors. The color filter patterns respectively disposed in four adjacent pixel areas and located in the first, the second, the third and the fourth sub-pixel regions adjacent to each other and arranged in the clockwise direction have the same color.

Abstract: The invention provides a non-volatile memory apparatus and an erasing method thereof The non-volatile memory apparatus includes a plurality of memory sectors and a control voltage provider. The memory sectors disposed in a same well, wherein, each of the memory sectors includes a plurality of memory cells for respectively receiving a plurality of control line signals. The control voltage provider provides the control line signals to the memory cells of each of the first memory sectors. When an erasing operation is operated, one of the memory sectors is selected for erasing and the control voltage provider provides the control line signals of the selected memory sector with an erase control voltage and provides the control line signals of the un-selected memory sectors with a un-erase control voltage, voltage levels of the erase control voltage and the un-erase control voltage are different.

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a substrate, a memory device, and a select transistor. The memory device is located on the substrate. The select transistor is located on the substrate and electrically connected to the memory device. The select transistor includes a select gate, a first dielectric layer, and a second dielectric layer. The select gate is located on the substrate. The first dielectric layer is adjacent to the second dielectric layer, and located between the select gate and the substrate. The first dielectric layer is closer to the memory device than the second dielectric layer. The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

Abstract: A thin heating device is provided. The thin heating device includes a first circuit board, a second circuit board, an elastic connector and a heating element. The first and second circuit boards are face-to-face arranged. The elastic connector connects the first and second circuit boards to apply a return force to hold an under-tested device. The heating element is mounted on the first or the second circuit board to heat the under-tested device.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer.

Abstract: A flip-lock type electrical device is provided. The flip-lock type electrical device includes a lid part which includes a metal part and a non-metal part, wherein the metal part includes a hinge cap, and one or a plurality of antennas, and one or a plurality of non-metal support material are configured in the hinge cape, and the hinge cape includes an antenna window, and wherein the antenna is grounded to the metal part, a main part, which includes a keyboard part and a base part, and a hinge part, configured to connect the lid part with the main part.

Abstract: A color filter substrate includes a transparent substrate and a plurality of color filter patterns. The transparent substrate has an upper surface and a lower surface opposite to each other, and a plurality of containing cavities. The containing cavities extend from the upper surface toward the lower surface and separate from each other. Each containing cavity has a bottom surface. The color filter patterns are disposed on the transparent substrate and located inside the containing cavities, respectively. The color filter patterns contact with the corresponding bottom surfaces, respectively.

Abstract: A color reflective display device includes a plurality of color sub-pixels and a control circuit. The control circuit is configured to provide a first driving signal to at least one of a plurality of mini-pixels of a first color sub-pixel, such that the at least one of mini-pixels receiving the first driving signal displays a first color, provide a second driving signal to another at least one of the mini-pixels of the first color sub-pixel, such that the another at least one of the mini-pixels receiving the second driving signal displays a second color, and provide a third driving signal to a second color sub-pixel of the color sub-pixels, such that the second color sub-pixel displays a third color.

Abstract: Using an adaptive square mesh for parasitic extraction, small squares of a predetermined minimum size will be placed where accuracy in the parasitic calculations is most critical—around edges, contacts and vias, and corners. Then, in areas where the parasitic analysis is less critical, for example in open spaces, a more coarse grid consisting of larger squares may be used to calculate the parasitic values in those spaces. Squares in the mesh may increase in size gradually to provide more accurate results.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer.

Abstract: A mobile apparatus, a base station, a direct communication system and a power control method thereof are provided. The direct communication system includes the mobile apparatus and the base station. The base station transmits a power measurement request message to the mobile apparatus. The mobile apparatus determines a power adjustment reference between the mobile apparatus and another mobile apparatus according to the power measurement request message. One of the mobile apparatus and the base station generates a power adjustment request message according to the power adjustment reference. The mobile apparatus adjusts a communication power with the another mobile apparatus according to the power adjustment request message.

Abstract: An apparatus with a handle having a release mechanism comprises a bracket having a front panel, an extracting module and a driven module. The extracting module is mounted on the bracket and includes a handle, an extracting piece, and a first contact portion. A spring is provided between the front panel and the extracting piece. The driven module is fixed on the bracket and includes a driven piece having a locking portion and a second contact portion. When the handle is not dragged forward, the locking portion is located in a locked position. When handle is dragged forward so that the extracting piece moves towards the front panel and that the first contact portion pushes the second contact portion, the locking portion is moved to an unlocked position. A system containing an apparatus having a handle is also provided.

Abstract: A method for fabrication a memory having a memory area and a periphery area is provided. The method includes forming a gate insulating layer over a substrate in the periphery area. Thereafter, a first conductive layer is formed in the memory area, followed by forming a buried diffusion region in the substrate adjacent to the sides of the first conductive layer. An inter-gate dielectric layer is then formed over the first conductive layer followed by forming a second conductive layer over the inter-gate dielectric layer. A transistor gate is subsequently formed over the gate insulating layer in the periphery area.

Abstract: An electrophoretic display panel including a transparent substrate, an active element array, a protective layer, plural electrophoretic display media and a transparent conductive layer is provided. The transparent substrate has an upper surface, a lower surface, plural first cavities located on the upper surface and plural second cavities located on the lower surface. The active element array is disposed on the upper surface and covers the upper surface and the first cavities. The protective layer is disposed on the upper surface and covers at least the active element array. The electrophoretic display media and the transparent conductive layer are disposed on the lower surface. The electrophoretic display media and the active element array overlap in at least a portion of their orthographic projections on the upper surface of the transparent substrate. The electrophoretic display media are located between the transparent conductive layer and the lower surface of the transparent substrate.

Abstract: The disclosure provides a color filter structure used to a reflective display. The color filter structure includes a transparent substrate, a plurality of color resists, a plurality of light-impermeable structures and a reflective layer. The transparent substrate has a top surface and a bottom surface, and the color resists are positioned on the top surface of the transparent substrate. The light-impermeable structures are positioned in the transparent substrate, in which the adjacent two color resists are separated by one of the light-impermeable structures. The reflective layer is positioned on the bottom surface of the transparent substrate. And the method for manufacturing the color filter structure is also disclosed herein.

Abstract: A field-effect transistor comprises a substrate, a gate dielectric layer, a barrier layer, a metal gate electrode and a source/drain structure. The gate dielectric layer is disposed on the substrate. The barrier layer having a titanium-rich surface is disposed on the gate dielectric layer. The metal gate electrode is disposed on the titanium-diffused surface. The source/drain structure is formed in the substrate and adjacent to the metal gate electrode.