Abstract: A clamping device for clamping silicon wafers of different sizes and cleaning same includes a main body and a plurality of clamping mechanisms. The surface of the main body defines a plurality of receiving grooves. Separate circular and concentric rows of clamping mechanisms are radially disposed around a central axis of the main body. The clamping mechanism includes first and second clamping members each received in one of the receiving grooves and are adjustable in respect of working height above or flush with the carrying surface of the main body. The first clamping member is closer to the center axis with respect to the second clamping member. A cleaning device with the clamping device is also disclosed.

Abstract: An extraction method of Hibiscus sabdariffa L. ‘TAITUNG NO. 6’, a Hibiscus sabdariffa L. ‘TAITUNG NO. 6’ extract using the same, and uses thereof are provided. The extraction method includes: providing the Hibiscus sabdariffa L. ‘TAITUNG NO. 6’ that is dried as a raw material for extraction; pulverizing the raw material; mixing the raw material that is pulverized with an extraction solvent for primary extraction, so as to obtain a Hibiscus sabdariffa L. ‘TAITUNG NO. 6’ primary extract; performing ultrasonic extraction on the Hibiscus sabdariffa L. ‘TAITUNG NO. 6’ primary extract, so as to obtain a Hibiscus sabdariffa L. ‘TAITUNG NO. 6’ extract; and filtering the Hibiscus sabdariffa L. ‘TAITUNG NO. 6’ extract.

Abstract: An isolation structure of a semiconductor device includes a substrate, a first isolation structure and a second isolation structure. The substrate has a first region and a second region, and there is a boundary between the first region and the second region. The first isolation structure is disposed in the first region of the substrate, and the first isolation structure includes a dielectric liner and a first insulating layer. The second isolation structure is disposed in the second region of the substrate, and the second isolation structure includes a second insulating layer. The first isolation structure and the second isolation structure are respectively located on both sides of the boundary.

Abstract: A semiconductor device with a deep trench isolation and a shallow trench isolation includes a substrate. The substrate is divided into a high voltage transistor region and a low voltage transistor region. A deep trench is disposed within the high voltage transistor region. The deep trench includes a first trench and a second trench. The first trench includes a first bottom. The second trench extends from the first bottom toward a bottom of the substrate. A first shallow trench and a second shallow trench are disposed within the low voltage transistor region. A length of the first shallow trench is the same as a length of the second trench. An insulating layer fills in the first trench, the second trench, the first shallow trench and the second shallow trench.

Abstract: A sampler circuit for use with a serial communication bus includes an amplifier circuit, an isolation circuit, and a latch circuit. During a first phase, the amplifier circuit amplifies a voltage difference between a first input signal and a second input signal received via the communication bus to generate a voltage difference on output nodes of the latch circuit. During an integration phase, the latch circuit increases the voltage difference on the output nodes. During a regeneration phase, the isolation circuit isolates the amplifier circuit from the latch circuit, which generates full-rail signals based on a voltage difference between the output nodes.

Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, and a light-sensing region close to the front surface. The image sensor device includes an insulating layer covering the back surface and extending into the semiconductor substrate. The protection layer has a first refractive index, and the first refractive index is less than a second refractive index of the semiconductor substrate and greater than a third refractive index of the insulating layer, and the protection layer conformally and continuously covers the back surface and extends into the semiconductor substrate. The image sensor device includes a reflective structure surrounded by insulating layer in the semiconductor substrate.

Abstract: A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.

Abstract: A surge protection circuit is presented. The surge protection circuit includes an input port for receiving an input voltage; an energy release cell having a first terminal coupled to the input port, a second terminal coupled to ground, and a control terminal coupled to the input port via a first switch device and to the ground via a second switch device. The surge protection circuit is adapted to close the first switch device to enable a current to flow from the input port to ground through the release cell upon occurrence of a positive voltage surge and to close the second switch device to enable a current to flow from ground to the input port through the release cell upon occurrence of a negative voltage surge.

Abstract: A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.

Abstract: A test method includes: generating an error correction code according to a base data; dividing the base data into a plurality of base data sections; generating a plurality of candidate testing data according to the base data, wherein each of the candidate testing data has a plurality of testing data sections, and each of the testing data sections corresponds to each of the base data sections; and, performing a plurality of testing schemes. Each of the testing schemes includes: generating a plurality of write-in test data according to the plurality of candidate testing data, and writing the plurality of write-in test data with the error correction code into a tested device continuously; reading a plurality of mode register values of the tested device and a plurality of readout data from the tested device; and generating a test result according to the plurality of mode register value and the readout data.

Abstract: A surge protection circuit is presented. The surge protection circuit includes an input port for receiving an input voltage; an energy release cell having a first terminal coupled to the input port, a second terminal coupled to ground, and a control terminal coupled to the input port via a first switch device and to the ground via a second switch device. The surge protection circuit is adapted to close the first switch device to enable a current to flow from the input port to ground through the release cell upon occurrence of a positive voltage surge and to close the second switch device to enable a current to flow from ground to the input port through the release cell upon occurrence of a negative voltage surge.

Abstract: A picture display method includes receiving a game picture of a target game from a target container in a process of running the target game, the target game being a cloud game running on the target container; obtaining a control operation on the target game performed on the terminal device, and locally drawing an operation animation according to the control operation; and superposing the operation animation on the received game picture, and displaying, on a user interface, the game picture on which the operation animation is superposed.

Abstract: A clamping device for clamping silicon wafers of different sizes and cleaning same includes a main body and a plurality of clamping mechanisms. The surface of the main body defines a plurality of receiving grooves. Separate circular and concentric rows of clamping mechanisms are radially disposed around a central axis of the main body. The clamping mechanism includes first and second clamping members each received in one of the receiving grooves and are adjustable in respect of working height above or flush with the carrying surface of the main body. The first clamping member is closer to the center axis with respect to the second clamping member. A cleaning device with the clamping device is also disclosed.

Abstract: Net-based checking of a circuit design includes obtaining a circuit design comprising a plurality of polygons. Further, a shape of a first polygon of the plurality of polygons, and a shape of a second polygon of the plurality of polygons is determined. The shape of the first polygon differs from a shape of the second polygon. Violations within the circuit design are detected based on a comparison of the first polygon with the second polygon.

Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, and a light-sensing region close to the front surface. The image sensor device includes an insulating layer covering the back surface and extending into the semiconductor substrate. The protection layer has a first refractive index, and the first refractive index is less than a second refractive index of the semiconductor substrate and greater than a third refractive index of the insulating layer, and the protection layer conformally and continuously covers the back surface and extends into the semiconductor substrate. The image sensor device includes a reflective structure surrounded by insulating layer in the semiconductor substrate.

Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.

Abstract: An LDMOS device comprises a well region, first and second implant regions, a gate electrode, first and second source/drain regions, a first STI region, and a first DTI region. The well region is in a substrate and of a first conductivity type. The first implant region is in the substrate and of a second conductivity type. The second implant region is in the well region and of the first conductivity type. The gate electrode extends from above the well region to above the first implant region. The first and second source/drain regions are respectively in the first and second implant regions. The first STI region laterally extends from the second implant region to directly below the gate electrode. The first DTI region extends downwards from a bottom surface of the first STI region into the well region. The first DTI region vertically overlaps with the gate electrode.

Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a first side, a second side opposite to the first side, and at least one light-sensing region close to the first side. The image sensor device includes a dielectric feature covering the second side and extending into the semiconductor substrate. The dielectric feature in the semiconductor substrate surrounds the light-sensing region. The image sensor device includes a reflective layer in the dielectric feature in the semiconductor substrate, wherein a top portion of the reflective layer protrudes away from the second side, and a top surface of the reflective layer and a top surface of the insulating layer are substantially coplanar.

Abstract: A physiological monitoring system is provided. The physiological monitoring system includes a feature extraction device, an identifier, a processor, a physiological sensing device, and a vital-sign detector. The feature extraction device extracts biological information of an object to generate an extraction signal. The identifier receives the extraction signal and verifies an identity of the object according to the extraction signal. The processor receives the extraction signal and obtains at least one biological feature of the user according to the extraction signal. The physiological sensing device senses a physiological feature to generate a bio-signal. The vital-sign detector estimates vital-sign data of the object according to the bio-signal and the at least one biological feature.

Abstract: A physiological monitoring system is provided. The physiological monitoring system includes a feature extraction device, an identifier, a processor, a physiological sensing device, and a vital-sign detector. The feature extraction device extracts biological information of an object to generate an extraction signal. The identifier receives the extraction signal and verifies an identity of the object according to the extraction signal. The processor receives the extraction signal and obtains at least one biological feature of the user according to the extraction signal. The physiological sensing device senses a physiological feature to generate a bio-signal. The vital-sign detector estimates vital-sign data of the object according to the bio-signal and the at least one biological feature.