Patents by Inventor Yuan Yin
Yuan Yin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11946349Abstract: A downhole throttling device based on wireless control includes an inlet nozzle, a throttling assembly, an electrical sealing cylinder, a gas guide cylinder, a lower adapter sleeve, an end socket, a female sleeve, and electrical components. The inlet nozzle is connected to the throttling assembly, the throttling assembly is connected to the electrical sealing cylinder and the gas guide cylinder, the electrical sealing cylinder and the gas guide cylinder are both connected to the lower adapter sleeve, the lower adapter sleeve is respectively connected to the end socket and the female sleeve, and the electrical components are arranged in the electrical sealing cylinder. A throttling effect is achieved by detecting the temperature and pressure in a tube by a temperature/pressure sensor in the electrical components and controlling a motor to rotate a movable valve in the throttling assembly by a circuit control assembly, thereby achieving wireless control over downhole throttling.Type: GrantFiled: September 15, 2020Date of Patent: April 2, 2024Assignees: PetroChina Company Limited, Sichuan Shengnuo Oil. And Gas Engineering Technology Service Co., LtdInventors: Jun Xie, Huiyun Ma, Jian Yang, Chenggang Yu, Yukun Fu, Qiang Yin, Kui Li, Yuan Jiang, Dezheng Yi, Yanyan Liu, Haifeng Zhong, Xiaodong Liu
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Publication number: 20240105814Abstract: A first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. The first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. The second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. A source/drain trench is formed in a region of the stack to expose side surfaces of the layers. A first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. A spacer is formed in the gap. A source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Inventors: Che-Lun Chang, Jiun-Ming Kuo, Ji-Yin Tsai, Yuan-Ching Peng
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Patent number: 11932478Abstract: A method for manufacturing and packaging a special-shaped cigarette includes the following steps: designing inner packaging case paper capable of being folded into a special-shaped cigarette accommodating cavity; folding the inner packaging case paper to form the special-shaped cigarette accommodating cavity; filling an interior of the special-shaped cigarette accommodating cavity with an ordinary cigarette; and shelving for a certain period of time, so that a cross section of the ordinary cigarette changes from a circle to a special shape, and the ordinary cigarette is accommodated in the special-shaped cigarette accommodating cavity. A diameter of an inscribed circle of the special-shaped cigarette accommodating cavity is less than a diameter of the ordinary cigarette, and a material of the inner packaging case paper is a paperboard or a food grade PVC sheet.Type: GrantFiled: November 2, 2021Date of Patent: March 19, 2024Assignee: CHINA TOBACCO YUNNAN INDUSTRIAL CO., LTDInventors: Xi Yang, Yuan Tian, Ying Wu, Fangrui Chen, Zhijiang Yin
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Publication number: 20240087879Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
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Publication number: 20240083667Abstract: A method for manufacturing and packaging a special-shaped cigarette includes the following steps: designing inner packaging case paper capable of being folded into a special-shaped cigarette accommodating cavity; folding the inner packaging case paper to form the special-shaped cigarette accommodating cavity; filling an interior of the special-shaped cigarette accommodating cavity with an ordinary cigarette; and shelving for a certain period of time, so that a cross section of the ordinary cigarette changes from a circle to a special shape, and the ordinary cigarette is accommodated in the special-shaped cigarette accommodating cavity. A diameter of an inscribed circle of the special-shaped cigarette accommodating cavity is less than a diameter of the ordinary cigarette, and a material of the inner packaging case paper is a paperboard or a food grade PVC sheet.Type: ApplicationFiled: November 2, 2021Publication date: March 14, 2024Applicant: CHINA TOBACCO YUNNAN INDUSTRIAL CO., LTDInventors: Xi YANG, Yuan TIAN, Ying WU, Fangrui CHEN, Zhijiang YIN
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Publication number: 20240078441Abstract: A method for knowledge representation and deduction of service logic includes: generating, based on a knowledge representation model, a semantic graph corresponding to conceptual-layer service logic, where the semantic graph includes one or more types of nodes and edges for connecting the one or more types of nodes, and the nodes include at least a node of a variable type; generating, based on the semantic graph and a physical table to which a service object is mapped, an instance graph, where the instance graph includes the nodes and edges in the semantic graph; generating executable code based on a service logic relationship between the nodes in the instance graph; and determining, based on the executable code and a data instance corresponding to a node whose in-degree is 0 in the instance graph, a data instance corresponding to each node in the instance graph.Type: ApplicationFiled: November 9, 2023Publication date: March 7, 2024Inventors: Rong Duan, Kangxing Hu, Wenwen Huang, Yuan Yuan, Wen Peng, Chunxi Liu, Qinjie Yang, Xiaoliang Yin, Shufan Li
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Publication number: 20240069267Abstract: The disclosure provides an optical waveguide assembly. The optical waveguide assembly includes: optical waveguide plates, where there are a plurality of optical waveguide plates, the plurality of optical waveguide plates are provided in an overlaid manner, each optical waveguide plate is provided with an in-coupling structure, a turning structure, an out-coupling structure and a diffraction inhibition layer, the turning structure and the out-coupling structure on the same optical waveguide plate are located on two side surfaces of the optical waveguide plate respectively, projections of the turning structure and the out-coupling structure on the optical waveguide plate are at least partially overlapped, and the diffraction inhibition layer is located between the out-coupling structure and the optical waveguide plate. Each turning structure includes a plurality of cellular elements. The disclosure solves a problem of non-uniform display efficiency of an optical waveguide assembly in the related art.Type: ApplicationFiled: March 29, 2023Publication date: February 29, 2024Inventors: Yifeng GAO, Zhengkun YIN, Linghe XIONG, Shenwu YANG, Qingwen ZHANG, Jie WANG, Yuan CHEN
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Patent number: 11917678Abstract: The present disclosure relates to computer-implemented systems and methods for facilitating simultaneous poll responses. A method may include assigning respective subsets of subcarrier frequencies to a plurality of user devices for communication over a wireless channel. The method may also include transmitting, simultaneously, a channel status request poll to the user devices. Additionally, the method may include determining, based at least in part on a first channel status response received via a first subset of subcarrier frequencies over the wireless channel, that the first channel status response is received from the first user device. Similarly, the method may also include determining a second channel status response is received from a second user device. Furthermore, the method may include determining, based at least in part on the first channel status response and the second channel status response, to schedule simultaneous data communication for the first device and the second device.Type: GrantFiled: July 12, 2018Date of Patent: February 27, 2024Assignee: Intel CorporationInventors: Qinghua Li, Po-Kai Huang, Hujun Yin, Xiaogang Chen, Yuan Zhu, Xintian Lin
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Publication number: 20240002394Abstract: The present disclosure provides a deuterium-modified thienopyridone compound, a preparation method therefor, a pharmaceutical composition thereof, and a medical use thereof. The deuterium-modified thienopyridone compound is shown in formula I, and has been shown to inhibit HPK1 kinase activity, being capable of achieving an anti-tumour effect.Type: ApplicationFiled: November 24, 2021Publication date: January 4, 2024Inventors: Yinsheng ZHANG, Yong GAO, Yuan YIN, Wei SHI, Damin ZHAO, Gaoyuan ZHU, Xiaojin WANG, Yanpeng JI
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Publication number: 20230357242Abstract: Provided is a compound as an Akt kinase inhibitor. The present invention specifically relates to a compound of formula (I) or a pharmaceutically acceptable salt thereof, a preparation method therefor, a pharmaceutical composition containing the compound, and the use thereof in the preparation of a drug for treating Akt kinase-related diseases.Type: ApplicationFiled: September 30, 2021Publication date: November 9, 2023Inventors: Yinsheng ZHANG, Yong GAO, Wei SHI, Damin ZHAO, Yuan YIN
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Publication number: 20230187409Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.Type: ApplicationFiled: February 9, 2023Publication date: June 15, 2023Applicant: Industrial Technology Research InstituteInventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Chao-Jung Chen, Tzu-Hsuan Ni, Shin-Yi Huang, Yuan-Yin Lo
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Patent number: 11646270Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.Type: GrantFiled: October 8, 2020Date of Patent: May 9, 2023Assignee: Industrial Technology Research InstituteInventors: Ang-Ying Lin, Yu-Min Lin, Shin-Yi Huang, Sheng-Tsai Wu, Yuan-Yin Lo, Tzu-Hsuan Ni, Chao-Jung Chen
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Patent number: 11587905Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.Type: GrantFiled: October 8, 2020Date of Patent: February 21, 2023Assignee: Industrial Technology Research InstituteInventors: Yu-Min Lin, Ang-Ying Lin, Sheng-Tsai Wu, Chao-Jung Chen, Tzu-Hsuan Ni, Shin-Yi Huang, Yuan-Yin Lo
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Patent number: 11569217Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.Type: GrantFiled: January 5, 2022Date of Patent: January 31, 2023Assignee: Industrial Technology Research InstituteInventors: Sheng-Tsai Wu, Yu-Min Lin, Yuan-Yin Lo, Ang-Ying Lin, Tzu-Hsuan Ni, Chao-Jung Chen, Shin-Yi Huang
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Patent number: 11479689Abstract: The present disclosure provides an anti-fogging material and a manufacturing method thereof. The anti-fogging material includes a crosslinked polymer obtained by curing an anti-fogging composition, wherein the anti-fogging composition includes an ionic compound, a hard compound with two or more acrylate functional groups at the terminus thereof, and a surface active compound.Type: GrantFiled: December 31, 2020Date of Patent: October 25, 2022Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Li-Ching Wang, Yuan-Yin Chen
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Patent number: 11424190Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via penetrating through the dielectric body, and a wiring structure located in each of the plurality of semiconductor bodies; a plurality of semiconductor chips located side by side on a first surface of the interposer and electrically connected to the wiring structure; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface of the interposer and electrically connected to the plurality of semiconductor chips through the through via.Type: GrantFiled: August 27, 2020Date of Patent: August 23, 2022Assignee: Industrial Technology Research InstituteInventors: Chao-Jung Chen, Yu-Min Lin, Sheng-Tsai Wu, Shin-Yi Huang, Ang-Ying Lin, Tzu-Hsuan Ni, Yuan-Yin Lo
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Publication number: 20220204804Abstract: The present disclosure provides an anti-fogging material and a manufacturing method thereof. The anti-fogging material includes a crosslinked polymer obtained by curing an anti-fogging composition, wherein the anti-fogging composition includes an ionic compound, a hard compound with two or more acrylate functional groups at the terminus thereof, and a surface active compound.Type: ApplicationFiled: December 31, 2020Publication date: June 30, 2022Inventors: Li-Ching Wang, Yuan-Yin Chen
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Publication number: 20220130812Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.Type: ApplicationFiled: January 5, 2022Publication date: April 28, 2022Applicant: Industrial Technology Research InstituteInventors: Sheng-Tsai Wu, Yu-Min Lin, Yuan-Yin Lo, Ang-Ying Lin, Tzu-Hsuan Ni, Chao-Jung Chen, Shin-Yi Huang
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Patent number: 11288219Abstract: A USB switching circuit includes a first multiplexer, a second multiplexer coupled with the first multiplexer through transmission paths, and a voltage regulation circuit coupled with the first and second multiplexers. The first multiplexer distributes first data signals to the transmission paths according to first control signals. The second multiplexer distributes a second data signal to the transmission paths according to second control signals. The voltage regulation circuit sets a maximum voltage and a minimum voltage of the first data signals to corresponding to a common voltage. The maximum voltage of the first data signals is not higher than a maximum voltage of the second control signals, or the minimum voltage of the first data signals is not lower than a minimum voltage of the second control signals. The first data signals and the second data signal are generated according to different communication protocols.Type: GrantFiled: October 27, 2020Date of Patent: March 29, 2022Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Kai-Yuan Yin, Wen-Bin Wu, Leaf Chen, Bo-Yu Chen
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Patent number: D976852Type: GrantFiled: June 18, 2020Date of Patent: January 31, 2023Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Sheng-Tsai Wu, Hsin-Han Lin, Yuan-Yin Lo, Kuo-Shu Kao, Tai-Jyun Yu, Han-Lin Wu, Yen-Ting Lin