Patents by Inventor Yuan Yu

Yuan Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12044844
    Abstract: An calibration kit includes a base, a combination of calibration parts, and a manipulation part. The combination of calibration parts is disposed on the base and includes a first calibration part and a second calibration part. The first calibration part has a first calibration surface. The second calibration part has a second calibration surface. The first calibration part and the second calibration part are relatively movable in a movement direction and are movable relative to the base. The manipulation part is movably or rotatably disposed on the base. The manipulation part is configured to be operable to drive the first calibration part and the second calibration part to move in the movement direction relative to the base, so that the combination of calibration parts forms a three-dimensional calibration surface configuration through the first calibration surface and the second calibration surface.
    Type: Grant
    Filed: September 6, 2021
    Date of Patent: July 23, 2024
    Assignee: Qisda Corporation
    Inventors: Tzu-Huan Hsu, Po-Fu Wu, Yuan-Yu Hsiao, Ching-Huey Wang, Chih-Kang Peng, Chun-Ming Shen, Chih-Ming Hu, Yi-Ling Lo
  • Patent number: 12036551
    Abstract: The present disclosure provides a microfluidic device, including a bottom substrate, an electrowetting-on-dielectric (EWOD) chip, a circuit board, a dielectric film, and a motor. The EWOD chip is disposed on the bottom substrate, and the circuit board is arranged on the EWOD chip. The circuit board includes a circuit area that is electrically connected to the EWOD chip, and the empty area is adjacent to the circuit area and the EWOD chip is exposed. The dielectric film is disposed on the empty area of the circuit board and covers the exposed EWOD chip. The motor is disposed under the bottom substrate, and one end of the motor has a magnetic structure, so that the magnetic structure can move closer to or away from the bottom substrate.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: July 16, 2024
    Assignee: NATIONAL CHUNG CHENG UNIVERSITY
    Inventors: Shau-Chun Wang, Lai-Kwan Chau, Yuan-Yu Chen
  • Publication number: 20240230653
    Abstract: The present disclosure provides the use of BAZ1B_K426hy in the preparation of a product for tumor detection and belongs to the field of biotechnology. The present disclosure further provides a group of immunogenic polypeptides, including polypeptide A and polypeptide B. An anti-BAZ1B_K426hy polyclonal antibody is prepared by conducting mixed immunization on an animal with the immunogenic polypeptide. The polyclonal antibody can specifically recognize an endogenous protein BAZ1B_K426hy by enzyme-linked immunosorbent assay (ELISA)/Dot blot/Western blot, which is used for preparation of detection products for tumors and Williams syndrome.
    Type: Application
    Filed: April 14, 2023
    Publication date: July 11, 2024
    Applicants: Tangshan People's Hospital, North China University of Science and Technology, Tangshan Maternal And Child Health Hospital
    Inventors: Jingwu LI, Yufeng Li, Shuqing Wang, Jinghua Zhang, Jinghua Wu, Fen Hu, Yuan Yu, Yan Liu, Yuhui Li, Xuan Zheng
  • Publication number: 20240234400
    Abstract: Embodiments include a stacked semiconductor device and methods of forming the same. The stacked semiconductor device includes a first package embedded in a second package. Forming the first package includes mounting a first integrated circuit device to a first workpiece by a first set of solder connectors, depositing a first underfill between the first integrated circuit device and the first workpiece, and forming a first encapsulant laterally surrounding the first integrated circuit device. The first package is mounted to a second workpiece by a second set of solder connectors, a second underfill is deposited between the first package and the second workpiece, and a second encapsulant is deposited to laterally surround the first package.
    Type: Application
    Filed: January 10, 2023
    Publication date: July 11, 2024
    Inventors: Tsung-Yuan Yu, Tzuan-Horng Liu
  • Publication number: 20240234375
    Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via.
    Type: Application
    Filed: February 1, 2024
    Publication date: July 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Hsien Chiang, Hui-Chun Chiang, Tzu-Sung Huang, Ming-Hung Tseng, Kris Lipu Chuang, Chung-Ming Weng, Tsung-Yuan Yu, Tzuan-Horng Liu
  • Publication number: 20240210636
    Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.
    Type: Application
    Filed: March 5, 2024
    Publication date: June 27, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Publication number: 20240213036
    Abstract: A method for packaging a chip, the chip is packaged by disposing positioning post on the surface of the carrier, and the groove matching the positioning post is formed on the surface of the chip. During melting the first solder pastes and the second solder pastes , due to the interaction between the positioning post and the groove, the chip will not be deflected due to the tension of the first solder pastes and the second solder pastes, so that a chip packaging structure meets the expected requirements. The chip packaging structure is further provided in the present disclosure.
    Type: Application
    Filed: November 24, 2023
    Publication date: June 27, 2024
    Inventors: ZHI-YONG HUANG, YUAN-YU LIN
  • Publication number: 20240203898
    Abstract: An EM shielding structure for a semiconductor package is embedded in a through hole of a core layer of the semiconductor package. The EM shielding structure may include multiple vias formed by a copper plating operation. Additionally, a metal way surrounds the EM shielding structures and prevents, along with a dielectric material, unwanted EM radiation (passing through the vias) from emanating throughout the semiconductor package. The EM shielding structure can also take the form of an insert that is adhered to the core layer at a through hole of the core layer.
    Type: Application
    Filed: December 19, 2022
    Publication date: June 20, 2024
    Applicant: Avago Technologies International Sales Pte. Limited
    Inventors: Jin Seong CHOI, Hyunsuk Chun, Sampath Karikalan, Kwok Cheung Tsang, Wen Hsien Huang, Hsi-Wei Wang, Chia Yuan Yu
  • Publication number: 20240192456
    Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
    Type: Application
    Filed: February 26, 2024
    Publication date: June 13, 2024
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 12002799
    Abstract: A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, Hung-Yi Kuo, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Yuan Yu, Ming Hung Tseng
  • Publication number: 20240178102
    Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.
    Type: Application
    Filed: April 21, 2023
    Publication date: May 30, 2024
    Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
  • Publication number: 20240178150
    Abstract: A semiconductor device package structure is provided, including a redistribution structure, a first semiconductor device, a second semiconductor device, a bridge die, a first conductive bump, and a second conductive bump bumps, a third conductive bumps, and a first solder material. The first semiconductor device is disposed on a first side of the redistribution structure, the second semiconductor device and the bridge die are disposed on a second side opposite to the first side. The first conductive bump is disposed on the first semiconductor device, the second conductive bump is disposed on the second side of the redistribution structure and the third conductive bump is disposed on the second semiconductor device. The first solder material is electrically connected between the second conductive bump and the third conductive bump, and the redistribution structure is electrically connected between the first conductive bump and the second conductive bump.
    Type: Application
    Filed: January 19, 2023
    Publication date: May 30, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzuan-Horng LIU, Hao-Yi TSAI, Tsung-Yuan YU
  • Patent number: 11992290
    Abstract: A method of controlling an intraoral scanner includes upon completion of lighting a first projection device, triggering a second projection device to initiate lighting, upon initiation of lighting the first projection device, transmitting a first camera trigger signal, a first delay circuit delaying the first camera trigger signal until completion of lighting the second projection device, and upon receiving the first camera trigger signal, a first camera and a second camera starting exposing images.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: May 28, 2024
    Assignee: Qisda Corporation
    Inventors: Yuan-Yu Hsiao, Ching-Ting Liu
  • Publication number: 20240160948
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for receiving a request from a client to process a computational graph; obtaining data representing the computational graph, the computational graph comprising a plurality of nodes and directed edges, wherein each node represents a respective operation, wherein each directed edge connects a respective first node to a respective second node that represents an operation that receives, as input, an output of an operation represented by the respective first node; identifying a plurality of available devices for performing the requested operation; partitioning the computational graph into a plurality of subgraphs, each subgraph comprising one or more nodes in the computational graph; and assigning, for each subgraph, the operations represented by the one or more nodes in the subgraph to a respective available device in the plurality of available devices for operation.
    Type: Application
    Filed: August 18, 2023
    Publication date: May 16, 2024
    Inventors: Paul A. Tucker, Jeffrey Adgate Dean, Sanjay Ghemawat, Yuan Yu
  • Patent number: 11971256
    Abstract: A guided cold-atom inertial sensor system comprises an atom trap integrated platform, a laser system, a magnetic field system, a control system, and a computing system. The laser system and magnetic field system are adapted to form a magneto-optical trap (MOT) about a suspended waveguide of the atom trap integrated platform made of membrane integrated photonics. After loading cold atoms from a MOT, the photonic atom trap integrated platform generates one-dimensional guided atoms with an evanescent field optical dipole trap (EF-ODT) along the optical waveguide to create guided atomic accelerometers/gyroscopes. Motion of atomic wavepackets in a superposition state is created along the guided atom geometry by way of state-dependent momentum kicks. The light-pulse sequence of guided atom interferometry splits, redirects, and recombines atomic wavepackets, which allows measurement of atom interference fringes sensitive to inertial forces via a probe laser.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: April 30, 2024
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Jongmin Lee, Grant Biedermann, Yuan-Yu Jau, Michael Gehl, Christopher Todd DeRose
  • Publication number: 20240133890
    Abstract: The present disclosure provides the use of BAZ1B_K426hy in the preparation of a product for tumor detection and belongs to the field of biotechnology. The present disclosure further provides a group of immunogenic polypeptides, including polypeptide A and polypeptide B. An anti-BAZ1B_K426hy polyclonal antibody is prepared by conducting mixed immunization on an animal with the immunogenic polypeptide. The polyclonal antibody can specifically recognize an endogenous protein BAZ1B_K426hy by enzyme-linked immunosorbent assay (ELISA)/Dot blot/Western blot, which is used for preparation of detection products for tumors and Williams syndrome.
    Type: Application
    Filed: April 13, 2023
    Publication date: April 25, 2024
    Applicants: Tangshan People's Hospital, North China University of Science and Technology, Tangshan Maternal And Child Health Hospital
    Inventors: Jingwu LI, Yufeng Li, Shuqing Wang, Jinghua Zhang, Jinghua Wu, Fen Hu, Yuan Yu, Yan Liu, Yuhui Li, Xuan Zheng
  • Publication number: 20240121920
    Abstract: A terminal device and a terminal device installation method are provided. The terminal device includes a machine body, a detachable cover with two side walls, and at least two coupling mechanisms arranged symmetrically. The machine body includes a front board, a rear board opposite to the front board, and two side boards connected between the front board and the rear board. Each coupling mechanism includes a coupling portion located at one side wall, a front track and a rear track respectively having a front opening and a rear opening opposite to the front opening and both located at one side board. As each coupling portion is coupled to each front track, the cover is assembled with the machine body and covers the front board, and as each coupling portion is coupled with each rear track, the cover is assembled to the machine body and covers the rear board.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 11, 2024
    Inventors: Yuan-Yu CHEN, Ming-Hung HUNG, Po-Chang CHU
  • Publication number: 20240120679
    Abstract: A bracket and a terminal equipment are provided. The bracket is provided for a terminal device to be installed thereon and includes a bracket body, two installing elements, and at least one holding element. The two installing elements respectively protrude outward from two sides of the bracket body, and each of the two installing elements includes an engaging portion. The two installing elements are configured to be inserted into the terminal device so the terminal device is installed on the bracket, and each of the engaging portions is configured such that each of the installing elements is engaged with and retained in the terminal device. The holding element protrudes outward from the bracket body and is configured to be inserted into a loading hole of the terminal device.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 11, 2024
    Inventors: Yuan-Yu CHEN, Ming-Hung HUNG, Ying Chih LIU
  • Patent number: 11953740
    Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 11947173
    Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu