Abstract: A new self-routing multicast network that can realize arbitrary multicast (or one-to-many) communication without any blocking. Based on the binary radix sorting, all functional components of the network are recursively constructed reverse banyan networks using a self-routing procedure that provides for pipeline distribution of switch settings. The design allows a potential to greatly reduce the network cost by reusing part of the network. The new multicast network has O(n log2 n) cost (logic gates), O(log2 n) gate delay, and O(log2 n) set-up time, where the unit of time is a gate delay. Further, with feedback part of the network can be reused and the network cost is reduced to O(n log n).

Abstract: A controller for a nonblocking broadcast switching network comprising an input stage, an output stage, and a middle stage. The input stage has N.sub.1 or n.sub.1 r.sub.1 input ports and r.sub.1 switches, where n.sub.1 .gtoreq.2 and r.sub.1 .gtoreq.1 and are integers. The network also includes an output stage. The output stage has N.sub.2 or n.sub.2 r.sub.2 output ports and r.sub.2 switches, where n.sub.2 .gtoreq.2 and r.sub.1 .gtoreq.1 and are integers. There is also a middle stage. The middle stage has m switches, where ##EQU1## The m switches are in communication with the r.sub.1 switches and r.sub.2 switches. The middle stage of m switches has L inputs, where L.gtoreq.r.sub.1 and is an integer, and J outputs, where J.gtoreq.r.sub.2 and is an integer, corresponding to the n.sub.1 input ports and n.sub.2 output ports, x or fewer of the m switches, where 1.ltoreq.x.ltoreq.

Abstract: The present invention pertains to a nonblocking broadcast switching network. The network comprises an input stage. The input stage has N.sub.1 or n.sub.1 r.sub.1 input ports and r.sub.1 switches, where n.sub.1 .gtoreq.2 and r.sub.1 .gtoreq.1 and are integers. The network is also comprised of an output stage. The output stage has N.sub.2 or n.sub.2 r.sub.2 output ports and r.sub.2 switches, where n.sub.2 .gtoreq.2 and r.sub.1 .gtoreq.1 and are integers. There is also a middle stage. The middle stage has m switches where m is an integer and, where ##EQU1## The m switches are in communication with the r.sub.1 switches and r.sub.2 switches. The middle stage of m switches has L inputs, where L.gtoreq.r.sub.1 and is an integer, and J outputs, where J.gtoreq.r.sub.2 and is an integer, x or fewer of the m switches, where 1.gtoreq.x.gtoreq.min{n.sub.2 -1, r.sub.