Patents by Inventor Yuanyuan Yang

Yuanyuan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080107103
    Abstract: A k-source N1×N2 nonblocking multicast switching network has N1 input ports and N2 output ports with each port having k independent channels, in which each input channel can perform a multicast connection, i.e. send data simultaneously to multiple output channels, without interrupting existing multicast connections from other input channels. We provide the construction and the routing algorithm of a multi-source nonblocking multicast three-stage switching network. A k-source N1×N2 such a switching network consists of three stages of switch modules (which are k-source multicast switching networks with smaller sizes). It has r1 k-source n1×m switch modules in the input stage, m k-source r1×r2 switch modules in the middle stage, and r2 k-source m×n2 switch modules in the output stage with N1=n1r1 and N2=n2r2. There are exactly k channels (corresponding to one port of k-source switch module) between every two switch modules in two consecutive stages.
    Type: Application
    Filed: November 7, 2006
    Publication date: May 8, 2008
    Inventors: Yuanyuan Yang, Takashi Oguma
  • Publication number: 20050141804
    Abstract: Method and apparatus for performing group switching in DWDM optical networks are described. One embodiment is an N×N three-stage group connector with N inputs and N outputs, wherein the N outputs are divided into r output groups, each group including n outputs such that r=N/n. The group connector comprises a first stage comprising r n×m crossbar switch modules, wherein m?n?1; a second stage comprising m r×r crossbar switch modules; and a third stage comprising r M×N concentrator switch modules.
    Type: Application
    Filed: December 24, 2003
    Publication date: June 30, 2005
    Inventors: Yuanyuan Yang, Siqing Zheng, Dominique Verchere
  • Patent number: 6456838
    Abstract: Disclosed is a method for all-to-all personalized exchange for a class of multistage interconnecting networks (MINs). The method is based on a Latin square matrix corresponding to a set of admissible permutations of a multistage interconnecting network. Disclosed are first and second methods for constructing a Latin square matrix used in the personalized exchange technique. Also disclosed is a generic method for decomposing all-to-all personalized exchange patterns into admissible permutations to form the Latin square matrix for self-routing networks which are a subclass of the MINs.
    Type: Grant
    Filed: February 17, 1999
    Date of Patent: September 24, 2002
    Assignees: Verizon Laboratories Inc., The University of Vermont
    Inventors: Jianchao Wang, Yuanyuan Yang
  • Patent number: 6456620
    Abstract: Disclosed is a method for all-to-all personalized exchange for a class of multistage interconnecting networks (MINs). The method is based on a Latin square matrix corresponding to a set of admissible permutations of a multistage interconnecting network. Disclosed are first and second methods for constructing a Latin square matrix used in the personalized exchange technique. Also disclosed is a generic method for decomposing all-to-all personalized exchange patterns into admissible permutations to form the Latin square matrix for self-routing networks which are a subclass of the MINs.
    Type: Grant
    Filed: February 17, 1999
    Date of Patent: September 24, 2002
    Assignees: Verizon Laboratories Inc., The University of Vermont
    Inventors: Jianchao Wang, Yuanyuan Yang
  • Patent number: 6201808
    Abstract: A new self-routing multicast network that can realize arbitrary multicast (or one-to-many) communication without any blocking. Based on the binary radix sorting, all functional components of the network are recursively constructed reverse banyan networks using a self-routing procedure that provides for pipeline distribution of switch settings. The design allows a potential to greatly reduce the network cost by reusing part of the network. The new multicast network has O(n log2 n) cost (logic gates), O(log2 n) gate delay, and O(log2 n) set-up time, where the unit of time is a gate delay. Further, with feedback part of the network can be reused and the network cost is reduced to O(n log n).
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: March 13, 2001
    Assignees: Verizon Laboratories Inc., University of Vermont
    Inventors: Jianchao Wang, Yuanyuan Yang
  • Patent number: 5801641
    Abstract: A controller for a nonblocking broadcast switching network comprising an input stage, an output stage, and a middle stage. The input stage has N.sub.1 or n.sub.1 r.sub.1 input ports and r.sub.1 switches, where n.sub.1 .gtoreq.2 and r.sub.1 .gtoreq.1 and are integers. The network also includes an output stage. The output stage has N.sub.2 or n.sub.2 r.sub.2 output ports and r.sub.2 switches, where n.sub.2 .gtoreq.2 and r.sub.1 .gtoreq.1 and are integers. There is also a middle stage. The middle stage has m switches, where ##EQU1## The m switches are in communication with the r.sub.1 switches and r.sub.2 switches. The middle stage of m switches has L inputs, where L.gtoreq.r.sub.1 and is an integer, and J outputs, where J.gtoreq.r.sub.2 and is an integer, corresponding to the n.sub.1 input ports and n.sub.2 output ports, x or fewer of the m switches, where 1.ltoreq.x.ltoreq.
    Type: Grant
    Filed: September 18, 1995
    Date of Patent: September 1, 1998
    Assignee: The Johns Hopkins University
    Inventors: Yuanyuan Yang, Gerald M. Masson
  • Patent number: 5451936
    Abstract: The present invention pertains to a nonblocking broadcast switching network. The network comprises an input stage. The input stage has N.sub.1 or n.sub.1 r.sub.1 input ports and r.sub.1 switches, where n.sub.1 .gtoreq.2 and r.sub.1 .gtoreq.1 and are integers. The network is also comprised of an output stage. The output stage has N.sub.2 or n.sub.2 r.sub.2 output ports and r.sub.2 switches, where n.sub.2 .gtoreq.2 and r.sub.1 .gtoreq.1 and are integers. There is also a middle stage. The middle stage has m switches where m is an integer and, where ##EQU1## The m switches are in communication with the r.sub.1 switches and r.sub.2 switches. The middle stage of m switches has L inputs, where L.gtoreq.r.sub.1 and is an integer, and J outputs, where J.gtoreq.r.sub.2 and is an integer, x or fewer of the m switches, where 1.gtoreq.x.gtoreq.min{n.sub.2 -1, r.sub.
    Type: Grant
    Filed: October 19, 1993
    Date of Patent: September 19, 1995
    Assignee: The Johns Hopkins University
    Inventors: Yuanyuan Yang, Gerald M. Masson