Patents by Inventor Yueh-Se Ho

Yueh-Se Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050145996
    Abstract: A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
    Type: Application
    Filed: October 25, 2004
    Publication date: July 7, 2005
    Inventors: Leeshawn Luo, Anup Bhalla, Yueh-Se Ho, Sik Lui, Mike Chang
  • Patent number: 6909170
    Abstract: A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: June 21, 2005
    Assignee: Siliconix Incorporated
    Inventors: Mike Chang, King Owyang, Yueh-Se Ho, Y. Mohammed Kasem, Lixiong Luo, Wei-Bing Chu
  • Publication number: 20050127532
    Abstract: A semiconductor package includes a lead frame having a plurality of leads and a lead frame pad, the lead frame pad including a die coupled thereto, at least one of the plurality of leads having an external portion sloped upwards relative to a bottom surface of the package, metal connectors connecting the die to the plurality of leads, and a resin body encapsulating the die, metal connectors and at least a portion of the lead frame.
    Type: Application
    Filed: December 9, 2003
    Publication date: June 16, 2005
    Inventors: Leeshawn Luo, Anup Bhalla, Sik Lui, Yueh-Se Ho, Mike Chang, Xiao Zhang
  • Patent number: 6876061
    Abstract: A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate).
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: April 5, 2005
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Patent number: 6841852
    Abstract: A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: January 11, 2005
    Inventors: Leeshawn Luo, Anup Bhalla, Yueh-Se Ho, Sik K. Lui, Mike Chang
  • Patent number: 6744124
    Abstract: A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: June 1, 2004
    Assignee: Siliconix Incorporated
    Inventors: Mike Chang, King Owyang, Yueh-Se Ho, Y. Mohammed Kasem, Lixiong Luo, Wei-Bing Chu
  • Publication number: 20040004272
    Abstract: A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (110a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (110a) increases the number of interconnections between the metal area (110a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
    Type: Application
    Filed: July 2, 2002
    Publication date: January 8, 2004
    Inventors: Leeshawn Luo, Anup Bhalla, Yueh-Se Ho, Sik K. Lui, Mike Chang
  • Publication number: 20030183924
    Abstract: This invention discloses a method for configuring a power MOSFET package by packaging several paralleled and separated MOSFET chips in the assembly. The method further includes a step of connecting the gate pad on each of these MOSFET chips with a low-resistance gate bus. The package resistance and inductance are significantly reduced and switching speed and heat dissipation are substantially improved.
    Type: Application
    Filed: July 30, 2002
    Publication date: October 2, 2003
    Applicant: Alpha & Omega Semiconductor, LTD.
    Inventors: Anup Bhalla, Sik K. Lui, Leeshawn Luo, Yueh-Se Ho
  • Patent number: 6562647
    Abstract: A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate).
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: May 13, 2003
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Publication number: 20030057532
    Abstract: A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.
    Type: Application
    Filed: November 7, 2002
    Publication date: March 27, 2003
    Inventors: Mike Chang, King Owyang, Yueh-Se Ho, Y. Mohammed Kasem, Lixiong Luo, Wei-Bing Chu
  • Publication number: 20020185710
    Abstract: A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate).
    Type: Application
    Filed: May 28, 2002
    Publication date: December 12, 2002
    Applicant: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Patent number: 6441475
    Abstract: This semiconductor surface mount package is relatively inexpensive to produce and has a footprint that is essentially the same size as the die. A conductive substrate is attached to the back side of a wafer and is in electrical contact with a terminal on the back side of each die in the wafer. A nonconductive overcoat is formed and patterned on the front side of the wafer, leaving a portion of the passivation layer and the connection pads for the dice exposed, each of the connection pads being coated with a solderable metal layer. The assembly is then sawed in perpendicular directions along the scribe lines between the dice, but the saw cuts do not extend all the way through the substrate, which remains intact at its back side. The parallel cuts in one direction are broken to produce die strips which are mounted, sandwich-like, in a stack, with one side of the strips exposed.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: August 27, 2002
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Patent number: 6392290
    Abstract: In a semiconductor package for a chip having terminals on both sides, for example, a power MOSFET in which the gate and source terminals are on the front side and the drain terminal is on the back side, electrical contact is made with the back side terminal by extending vias, which can take the form of trenches, holes or other cavities, either entirely or patrially through the chip. The vias are filled with a metal or other electrically conductive material. The process is performed on the chips in a wafer simultaneously. The resulting package is compact and economical to manufacture and can readily be mounted, flip-chip style, on a printed circuit board.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: May 21, 2002
    Assignee: Siliconix Incorporated
    Inventors: Y. Mohammed Kasem, Yueh-Se Ho, Lee Shawn Luo, Chang-Sheng Chen, Eddy Tjhia, Bosco Lan, Jacek Korec, Anup Bhalla
  • Patent number: 6316287
    Abstract: A package for a semiconductor device is formed by a process which includes forming a metal layer in contact with a connection pad on the front side of a semiconductor die while the die is still a part of a wafer. The metal layer extends into the scribe line between the die and an adjacent die. A nonconductive cap is attached to the front side of the wafer, and the wafer is ground from its back side to reduce its thickness. A cut is made from the back side of the wafer, preferably by sawing and etching, to expose the metal layer. A nonconductive layer is formed on the back side of the wafer and a second metal layer is deposited over the nonconductive layer, the second metal layer extending into the scribe line where it makes contact with the first metal layer through an opening in the nonconductive layer. Preferably, a solder post is formed on the second metal layer to allow the finished package to be mounted on a printed circuit board.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: November 13, 2001
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Publication number: 20010016369
    Abstract: A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate).
    Type: Application
    Filed: April 26, 2001
    Publication date: August 23, 2001
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Patent number: 6271060
    Abstract: This semiconductor surface mount package is relatively inexpensive to produce and has a footprint that is essentially the same size as the die. A conductive substrate is attached to the back side of a wafer and is in electrical contact with a terminal on the back side of each die in the wafer. A nonconductive overcoat is formed and patterned on the front side of the wafer, leaving a portion of the passivation layer and the connection pads for the dice exposed, each of the connection pads being coated with a solderable metal layer. The assembly is then sawed in perpendicular directions along the scribe lines between the dice, but the saw cuts do not extend all the way through the substrate, which remains intact at its back side. The parallel cuts in one direction are broken to produce die strips which are mounted, sandwich-like, in a stack, with one side of the strips exposed.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: August 7, 2001
    Assignee: Vishay Intertechnology, Inc.
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Publication number: 20010009298
    Abstract: A package for a semiconductor device is formed by a process which includes forming a metal layer in contact with a connection pad on the front side of a semiconductor die while the die is still a part of a wafer. The metal layer extends into the scribe line between the die and an adjacent die. A nonconductive cap is attached to the front side of the wafer, and the wafer is ground from its back side to reduce its thickness. A cut is made from the back side of the wafer, preferably by sawing and etching, to expose the metal layer. A nonconductive layer is formed on the back side of the wafer and a second metal layer is deposited over the nonconductive layer, the second metal layer extending into the scribe line where it makes contact with the first metal layer through an opening in the nonconductive layer. Preferably, a solder post is formed on the second metal layer to allow the finished package to be mounted on a printed circuit board.
    Type: Application
    Filed: February 23, 2001
    Publication date: July 26, 2001
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Patent number: 6249041
    Abstract: An improved semiconductor device is disclosed. In one embodiment, the semiconductor device includes a semiconductor chip with contact areas on the top or bottom surface. A first lead assembly, formed from a semi-rigid sheet of conductive material, has a lead assembly contact attached to one of the contact areas of the semiconductor chip. The first lead assembly also has at least one lead connected to and extending from the lead assembly contact. A second lead assembly, also formed from a semi-rigid sheet of conductive material, has a lead assembly contact attached to another one of the contact areas of the semiconductor chip. The second lead assembly also has at least one lead connected to and extending from the lead assembly contact. An encapsulant encloses the semiconductor chip, the lead assembly contact of the first lead assembly and the lead assembly contact of the second lead assembly.
    Type: Grant
    Filed: June 2, 1998
    Date of Patent: June 19, 2001
    Assignee: Siliconix Incorporated
    Inventors: Y. Mohammed Kasem, Anthony C. Tsui, Lixiong Luo, Yueh-Se Ho
  • Publication number: 20010000631
    Abstract: This semiconductor surface mount package is relatively inexpensive to produce and has a footprint that is essentially the same size as the die. A conductive substrate is attached to the back side of a wafer and is in electrical contact with a terminal on the back side of each die in the wafer. A nonconductive overcoat is formed and patterned on the front side of the wafer, leaving a portion of the passivation layer and the connection pads for the dice exposed, each of the connection pads being coated with a solderable metal layer. The assembly is then sawed in perpendicular directions along the scribe lines between the dice, but the saw cuts do not extend all the way through the substrate, which remains intact at its back side. The parallel cuts in one direction are broken to produce die strips which are mounted, sandwich-like, in a stack, with one side of the strips exposed.
    Type: Application
    Filed: December 8, 2000
    Publication date: May 3, 2001
    Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
  • Patent number: 5904525
    Abstract: A method for forming a trenched DMOS transistor with deep body regions that occupy minimal area on an epitaxial layer formed on a semiconductor substrate. A first oxide layer is formed over the epitaxial layer and patterned to define deep-body areas beneath which the deep body regions are to be formed. Next, diffusion-inhibiting regions of the first conductivity type are formed in each of the deep-body areas before forming a second oxide layer covering the deep-body areas and the remaining portion of the first oxide layer. Portions of the second oxide layer are then removed to expose the centers of the diffusion inhibiting regions, leaving the first oxide layer and oxide sidewall spacers from the second oxide layer to cover the peripheries of the diffusion-inhibiting regions. A deep-body diffusion of a second conductivity type is then performed, resulting in the formation of deep body regions in the epitaxial layer between the sidewall spacers.
    Type: Grant
    Filed: May 8, 1996
    Date of Patent: May 18, 1999
    Assignee: Siliconix incorporated
    Inventors: Fwu-Iuan Hshieh, Yueh-Se Ho, Bosco Lan, Jowei Dun