Abstract: A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction nitride-based Schottky diode is thus realized. In another embodiment, a protection circuit for a vertical GaN Schottky diode employs a silicon-based vertical PN junction diode connected in parallel to the GaN Schottky diode to divert reverse bias avalanche current.

Abstract: A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.

Abstract: A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between two or more adjacent chips on the wafer are removed to form relatively wide gaps. A conductive material is applied to the back side of the semiconductor chips and in the gaps. The conductive material in the gaps between two or more of the chips is then cut through leaving conductive material on the back side and on side walls of the two or more chips. As a result, the conductive material provides an electrical connection from the electrode on the back side of the chip to the front side of the chip.

Abstract: The present invention relates to a package for semiconductor device and the fabrication method for integrally encapsulating a whole semiconductor chip within a molding compound. In the semicondcutor device package, bonding pads distributed on the top of the chip are redistributed into an array of redistributed bonding pads located in an dielectric layer by utilizing the redistribution technique. The electrodes or signal terminals on the top of the semiconductor chip are connected to an electrode metal segment on the bottom of the chip by conductive materials filled in through holes formed in a silicon substrate of a semiconductor wafer. Furthermore, the top molding portion and the bottom molding portion seal the semiconductor chip completely, thus providing optimum mechanical and electrical protections.

Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.

Abstract: A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.

Abstract: This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.

Abstract: A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.

Abstract: A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package.

Abstract: A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.

Abstract: A virtually substrate-less composite power semiconductor device (VSLCPSD) and method are disclosed. The VSLCPSD has a power semiconductor device (PSD), a front-face device carrier (FDC) made out of a carrier material and an intervening bonding layer (IBL). Both carrier and IBL material can be conductive or non-conductive. The PSD has back substrate portion, front semiconductor device portion with patterned front-face device metallization pads and a virtually diminishing thickness TPSD. The FDC has patterned back-face carrier metallizations contacting the front-face device metallization pads, patterned front-face carrier metallization pads and numerous parallelly connected through-carrier conductive vias respectively connecting the back-face carrier metallizations to the front-face carrier metallization pads. The FDC thickness TFDC is large enough to provide structural rigidity to the VSLCPSD.

Abstract: This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.

Abstract: A virtually substrate-less composite power semiconductor device (VSLCPSD) and method are disclosed. The VSLCPSD has a power semiconductor device (PSD), a front-face device carrier (FDC) made out of a carrier material and an intervening bonding layer (IBL). Both carrier and IBL material can be conductive or non-conductive. The PSD has back substrate portion, front semiconductor device portion with patterned front-face device metallization pads and a virtually diminishing thickness TPSD. The FDC has patterned back-face carrier metallizations contacting the front-face device metallization pads, patterned front-face carrier metallization pads and numerous parallelly connected through-carrier conductive vias respectively connecting the back-face carrier metallizations to the front-face carrier metallization pads. The FDC thickness TFDC is large enough to provide structural rigidity to the VSLCPSD.

Abstract: A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package.

Abstract: A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top surface. A semiconductor chip disposed on the die pad. A metal plate connected to a top surface electrode of the chip having a bent extension terminated in the V groove in contact with at least one of the V groove sidewalls.

Abstract: A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed.

Abstract: This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.

Abstract: A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.

Abstract: A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package.

Abstract: An electronic package for containing at least a top packaging module vertically stacked on a bottom packaging module. Each of the packaging modules includes a semiconductor chip packaged and connected by via connectors and connectors disposed on a laminated board fabricated with a standard printed-circuit board process wherein the top and bottom packaging module further configured as a surface mountable modules for conveniently stacking and mounting to prearranged electrical contacts without using a leadframe. At least one of the top and bottom packaging modules is a multi-chip module (MCM) containing at least two semiconductor chips. At least one of the top and bottom packaging modules includes a ball grid array (BGA) for surface mounting onto the prearranged electrical contacts. At least one of the top and bottom packaging modules includes a plurality of solder bumps on one of the semiconductor chips for surface mounting onto the prearranged electrical contacts.