Abstract: A domino SRAM is provided with active pull-up PFET devices that overwhelm “slow to write but very fast to read” cells and allow the cells to recover from timing mismatch situations. This approach allows the traditional “bit select” clamp to actively control the “local select” through “wired-or” PFET pull-up transistors. Separate read and write global “bit line” pairs allow the read and write performance to be optimized independently.

Abstract: A pulse to static converter for SRAM in which the converter latch is comprised of two cross-coupled, complementary, FET pairs. The FETs of each pair are coupled drain to drain between a positive voltage source and ground. The output state of SRAM sense amplifier is coupled as an input to the grates of one FET pair and the state established by this input is latched via the cross coupling with the other FET pair.

Abstract: A late select circuit topology has pseudo-static circuits that provide fast dynamic circuit operation without the use of dynamic clock timing signals. An output from a selected set is enabled by the conjunction of bit line pulse and set select signal.

Abstract: A multi-port (e.g., two port) CMOS static random access memory (SRAM) with a local clock driver generating clocks for boundary latches. Local clocks select between address inputs clocked into the boundary latches. A read clock selects and latches a read address in the boundary latches. A second clock latches write addresses and, when appropriate, test data addresses.

Abstract: A SRAM sense amplifier timing circuit provides various delay settings for the sense amplifier enable signal (sae) and the sense amplifier reset signal (rse) in order to allow critical timing adjustments to be made for early mode, late mode conditions by varying the timing or with of the sense amplifier output pulse. These timing adjustments are programmable using scan in bits.

Abstract: Methods for designing a 6T SRAM cell having greater stability and/or a smaller cell size are provided. A 6T SRAM cell has a pair access transistors (NFETs), a pair of pull-up transistors (PFETs), and a pair of pull-down transistors (NFETs), wherein the access transistors have a higher threshold voltage than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “0” during access of the cell thereby increasing the stability of the cell, especially for cells during “half select.” Further, a channel width of a pull-down transistor can be reduced thereby decreasing the size of a high performance six transistor SRAM cell without effecting cell the stability during access. And, by decreasing the cell size, the overall design layout of a chip may also be decreased.

Abstract: A silicon on insulator (SOI) CMOS circuit, macro and integrated circuit (IC) chip. The chip or macro may include be an SRAM in partially depleted (PD) SOI CMOS. Most field effect transistors (FETs) do not have body contacts. FETs otherwise exhibiting a sensitivity to history effects have body contacts. The body contact for each such FET is connected to at least one other body contact. A back bias voltage may be provided to selected FETs.

Abstract: An SRAM array local clock generator has variable delay settings that are programmable via level scan bits. Program bits from the level scan operation are decoded and used to adjust the number of delay elements in the local clock generator path.

Abstract: A silicon on insulator (SOI) CMOS circuit, macro and integrated circuit (IC) chip. The chip or macro may include be an SRAM in partially depleted (PD) SOI CMOS. Most field effect transistors (FETs) do not have body contacts. FETs otherwise exhibiting a sensitivity to history effects have body contacts. The body contact for each such FET is connected to at least one other body contact. A back bias voltage may be provided to selected FETs.

Abstract: A sense amplifier for a memory device comprising: a first sensing stage comprising a first sensing device and a second sensing device operably connected to a first sense line and a second sense line respectively, to reduce the capacitive load on the first sense line and second sense line. A source terminal of the sensing device is connected to a switchable current sink with drain terminal thereof connected to an input of a second sensing stage. The sense amplifier also includes a second sensing stage comprising cross-coupled inverters responsive to the first sensing stage, the second sensing stage is activated by a sense enable signal following a selected delay, and an output driver responsive to the second sensing stage.

Abstract: A high performance CMOS comparator circuit is integrated with a bypass function allowing comparing first and second data sets (A & B) with a high data width (more than 30 and illustrated as 48 bits). In many cases, it is often required to compare not only sets A&B but also set A with an additional bypass set, and the preferred circuit embodiment permits this to be achieved.

Abstract: A memory sense amplifier includes a latch formed for interconnected CMOS gates with an input gate connected to one node of the latch and a reference gate connected to the other node of the latch the reference gate has an input connected to a source of reference voltage and the reference gate and input gate are activated in response to common enable signal. When the input signal, e.g., a data signal from a memory, has a signal value lower than the reference signal value when the two gates are enabled, the reference gate will discharge the node to which it is connected more rapidly than the input gate will discharge the other node. Due to the internal cross connections of the latch, the latch will rapidly change state so as to further discharge the node to which the reference is connected and further charge the other node.

Abstract: Output signals from a plurality of self reset CMOS a logic circuits are multiplexed by means of the plurality of input multiplex circuits and an output circuit. The multiplex circuits are individually enabled by means of a select lead and true and complement input signals to the multiplex circuits are supplied to input terminals of an output circuit in which the state of the true or complement input is latched to provide a static output. The inputs to the output circuits simultaneously provide an output and initiate the setting of the latch by means of a separate latch setting gate. An inverter tree within the output circuit maintains the state of the output on the output terminal of the output circuit after the latch has been reset. A test access to the output circuit allows a test signal to be gated into a test latch and subsequently gated into the primary latch of the output circuit to provide a test output.

Abstract: Output signals from a plurality of self reset CMOS a logic circuits are multiplexed by means of the plurality of input multiplex circuits and an output circuit. The multiplex circuits are individually enabled by means of a select lead and true and complement input signals to the multiplex circuits are supplied to input terminals of an output circuit in which the state of the true or complement input is latched to provide a static output. The inputs to the output circuits simultaneously provide an output and initiate the setting of the latch by means of a separate latch setting gate. An inverter tree within the output circuit maintains the state of the output on the output terminal of the output circuit after the latch has been reset. A test access to the output circuit allows a test signal to be gated into a test latch and subsequently gated into the primary latch of the output circuit to provide a test output.

Abstract: A memory and sense amplifier with latched output included therein derives high speed and noise immunity with precharged logic circuits through the separation of sense amplifier enablement and resetting by use of the precharge operation. Inclusion of bit line decoders which are wholly or partially self-resetting and self-precharging in sense amplifier support circuitry allows high performance at extremely short memory operation cycle times. A multiplexor is included which is usable in operating cycles as well as test cycles of the memory and further, in combination with other elements of the memory and sense amplifier arrangement, enables the pipelining of plural memory operations in a single memory cycle.

Abstract: A memory and sense amplifier with latched output included therein derives high speed and noise immunity with precharged logic circuits through the separation of sense amplifier enablement and resetting by use of the precharge operation. Inclusion of bit line decoders which are wholly or partially self-resetting and self-precharging in sense amplifier support circuitry allows high performance at extremely short memory operation cycle times. A multiplexor is included which is usable in operating cycles as well as test cycles of the memory and further, in combination with other elements of the memory and sense amplifier arrangement, enables the pipelining of plural memory operations in a single memory cycle.

Abstract: A bit decoder for a memory array includes a decode NOR/OR circuit coupled to an output driver circuit. The decode NOR/OR circuit includes a plurality of input signals connected to respective input FET's all of which are connected in parallel between a common source and a common drain node. One input is also connected to an active pullup FET which is connected in series with the input FET's at the common drain node and which is always maintained slightly on. A bipolar transistor pulls down the common drain node and a bleeder FET pulls down the common source node. The output driver is a BICMOS circuit that provides both the bit selection and bit refresh signals which are of opposite phase.

Abstract: A switchable voltage generator is provided on-chip together with circuitry including transistors formed in accordance with several different technologies and optimized for operation at different voltages. Provision of a voltage generator on the chip avoids the need for dedicated connections for the lower voltage or voltages. To provide similar levels of burn-in voltage to the different transistor types, a bypass or shunt is provided across the regulator of the voltage generator. The on-chip voltage generator avoids the requirement for a large number of chip or module power connections for each supply voltage required in order to meet current requirements of different portions of chip circuitry. The use of a mode select receiver also avoids the requirement of additional connections to the chip. The combination of one or more switchable voltage generators with a mode select receiver allows economical and efficient electrically stressed testing of the chip at different levels of manufacture.

Abstract: A word decoder for a memory array includes a decode NOR/OR circuit 52 coupled to an output driver circuit 54. Decode NOR/OR circuit 52 includes a plurality of input signals IN1, IN2, IN3 connected to respective input n-channel field effect transistor (NEFTs) N1, N2, N3, all of which are parallel to a common node 1. The first input IN1 is also connected to a an active pull-up p-channel field effect transistor (PFETs) P1 which is in series with the first NFET N1 and always maintained slightly on. A bipolar transistor T4 pulls down node 1 and a pair of bleeder NFETs N4, N5 pull down nodes 3 and 2, respectively. Output driver circuit 54 is comprised of bipolar transistors T1, T2, T3 arranged in a push-pull configuration.

Abstract: A push-pull driver circuit is disclosed comprising two stages. The first stage includes a current switch producing a dual phase output. The second stage includes a first emitter follower for output pull-up and a second emitter follower and a current mirror for output pull-down. The inputs of the first and second emitter followers are connected to respective output phases of the first stage. The outputs of the emitter followers are connected to respective terminals of the current mirror. The output of the second emitter follower also is connected to the output line being driven. A fixed biasing source maintains the current mirror transistors in conductive states at all times. Schottky diodes are connected to the current mirror transistors to prevent saturation.