Abstract: An optoelectronic device is disclosed, comprising: a photodiode array including a plurality of first photodiodes, each first photodiode including a respective n+ region and a respective n-well region; a guide array disposed over the photodiode array, the guide array including a plurality of guide members separated from one another by a layer of light-blocking material, the guide members being aligned with the n+ regions of the first photodiodes, such that each guide member is disposed over a different respective n+ region, and the layer of light-blocking material being aligned with the n-well regions of the first photodiodes; and a filter array disposed over the guide array, the filter array including a plurality of bandpass filters, each bandpass filter being aligned with a different one of the plurality of guide members, each bandpass filter having a different transmission band.

Abstract: Techniques for generating an indication of ambient light intensity are provided. The techniques include obtaining a set of one or more low light level measurements during a low light level display panel period of a display; obtaining a set of one or more high light level measurements during a high light level display panel period of the display; generating an ambient light level result based on analysis of the set of one or more low light level measurements, the set of one or more high light level measurements, and calibration information; and controlling brightness of the display based on the ambient light level result.

Abstract: Radio Frequency (RF) circuit (amplifiers, mixer, etc.) design with RFIC, e.g., implemented in CMOS, CaAs, SiGe, or other silicon processes, suffers performance variations (gain phase, frequency, bandwidth, nonlinearity) due to wafer process variations, temperature changes, and supply voltage changes, and random variations. In this invention, methods are proposed to precisely calibrate the bias current of all active devices in the system, and to precisely calibrate the gain of individual path leading to each amplifiers such that the same Pout is achieved for all antenna elements in the system.

Abstract: Techniques for generating an indication of ambient light intensity are provided. The techniques include obtaining a set of one or more low light level measurements during a low light level display panel period of a display; obtaining a set of one or more high light level measurements during a high light level display panel period of the display; generating an ambient light level result based on analysis of the set of one or more low light level measurements, the set of one or more high light level measurements, and calibration information; and controlling brightness of the display based on the ambient light level result.

Abstract: Techniques for generating an indication of ambient light intensity are provided. The techniques include obtaining a set of one or more low light level measurements during a low light level display panel period of a display; obtaining a set of one or more high light level measurements during a high light level display panel period of the display; and generating an ambient light level result based on analysis of the set of one or more low light level measurements, the set of one or more high light level measurements, and calibration information.

Abstract: A power amplifier (PA) linearization technique with a wider linearized power range is proposed. Proposed two types of linearizers with cross-coupled PMOS and NMOS configuration. The idea is to use a complimentary device compared with the PA core device, and the behavior of Cgs of the linearizer are also complimentary to the PA itself. In the other words, the overall Cgs of the PA with the linearizer would be constant without leading to non-linear waveform. Both linearizers can effectively compensate not only AMAM but also AMPM. First type of linearizer can be integrated with PA cores, and second type of linearizer can be used in the IMN. Both linearizers have effective IM3 reduction in different corner.

Abstract: An optoelectronic device is disclosed, comprising: a photodiode array including a plurality of first photodiodes, each first photodiode including a respective n+ region and a respective n-well region; a guide array disposed over the photodiode array, the guide array including a plurality of guide members separated from one another by a layer of light-blocking material, the guide members being aligned with the n+ regions of the first photodiodes, such that each guide member is disposed over a different respective n+ region, and the layer of light-blocking material being aligned with the n-well regions of the first photodiodes; and a filter array disposed over the guide array, the filter array including a plurality of bandpass filters, each bandpass filter being aligned with a different one of the plurality of guide members, each bandpass filter having a different transmission band.

Abstract: An optoelectronic device is disclosed, comprising: a photodiode array including a plurality of first photodiodes, each first photodiode including a respective n+ region and a respective n-well region; a guide array disposed over the photodiode array, the guide array including a plurality of guide members separated from one another by a layer of light-blocking material, the guide members being aligned with the n+ regions of the first photodiodes, such that each guide member is disposed over a different respective n+ region, and the layer of light-blocking material being aligned with the n-well regions of the first photodiodes; and a filter array disposed over the guide array, the filter array including a plurality of bandpass filters, each bandpass filter being aligned with a different one of the plurality of guide members, each bandpass filter having a different transmission band.

Abstract: An optoelectronic device is disclosed, comprising: a photodiode array including a plurality of first photodiodes, each first photodiode including a respective n+ region and a respective n-well region; a guide array disposed over the photodiode array, the guide array including a plurality of guide members separated from one another by a layer of light-blocking material, the guide members being aligned with the n+ regions of the first photodiodes, such that each guide member is disposed over a different respective n+ region, and the layer of light-blocking material being aligned with the n-well regions of the first photodiodes; and a filter array disposed over the guide array, the filter array including a plurality of bandpass filters, each bandpass filter being aligned with a different one of the plurality of guide members, each bandpass filter having a different transmission band.

Abstract: A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

Abstract: A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

Abstract: A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

Abstract: A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

Abstract: A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

Abstract: A gap-filling dielectric layer, method for fabricating the same and applications thereof are disclosed. A silicon-containing dielectric layer is firstly deposited on a substrate. The silicon-containing dielectric layer is then subjected to a curing process, an in-situ wetting treatment and an annealing process in sequence, whereby a gap-filling dielectric layer with a nitrogen atom density less than 1×1022 atoms/cm3 is formed.

Abstract: An optical sensor system is disclosed. The optical sensor system comprises a panel and a sensing unit. The panel comprises a plurality of transparent areas. The sensing unit locates at one side of the panel and the sensing unit senses a plurality of first light signals reflected by an object and senses a plurality second light signals of an ambient light. The reflected first light signals and the second light signals pass through one of the plurality of transparent areas of the panel. The sensing unit further comprises a light sensor and a plurality of gesture sensors. The light sensor locates at the center of the sensing unit, and the light sensor senses the second light signals. The plurality of gesture sensors surrounds the light sensor, and the gesture sensors senses the reflected first light signals and then produce gesture signals corresponding to motions of the object.

Abstract: A method for forming an interlevel dielectric (ILD) layer includes the following steps. A MOS transistor on a substrate is provided. A first undoped oxide layer is deposited to cover the substrate and the MOS transistor. The first undoped oxide layer is planarized. A phosphorus containing oxide layer is deposited on the first undoped oxide layer. A second undoped oxide layer is deposited on the phosphorus containing oxide layer.

Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.

Abstract: A selectable view angle optical sensor is disclosed. The selectable view angle optical sensor comprises a substrate, a photodiode array disposed on the substrate, a first optical shielding modulation layer disposed on a first plane and a second optical shielding modulation layer disposed on a second plane. The first plane is on the photodiode array, the second plane is on the first plane, and the first and second planes and a top surface of the photodiode array are substantially in parallel. The dimensions and configurations of the first and second optical shielding modulation layers limit a field of view of the photodiode array so that the photodiode array has selectable view angle function.

Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.