Abstract: Disclosed are a display substrate. The display substrate includes a drive backplane; a first electrode layer disposed on a side of the drive backplane; a pixel definition layer disposed on a side, distal to the drive backplane, of the first electrode layer; an organic light-emitting layer disposed on a side, distal to the drive backplane, of the pixel definition layer, wherein the organic light-emitting layer comprises: a plurality of organic material layers stacked in a direction perpendicular to and away from the drive backplane, and a portion of the organic material layer disposed inside the partition groove is separated from a portion of the organic material layer disposed outside the partition groove; and a second electrode layer disposed on a side, distal to the drive backplane, of the organic light-emitting layer.

Abstract: In some embodiments, an apparatus includes a housing defining an interior space, a sensor, and a processor. The sensor is configured to sense an indication generated by a compute device. The indication can be at least one of a visual indication, an auditory indication, or a vibratory indication. The processor can be configured to determine whether to transition a lock status of the apparatus from locked to unlocked based on the indication sensed by the sensor. The processor can initiate a transition of the lock status from locked to unlocked upon determining to transition the lock status.

Abstract: An organic field-effect transistor and a fabrication method therefor, including: providing a gate; depositing polymer material onto the gate to form a dielectric layer; performing supercritical fluids treatment on the gate having the dielectric layer deposited; depositing organic semiconductor layer material on the dielectric layer having been processed, to form an organic semiconductor layer; depositing electrode layer material on the organic semiconductor layer and forming an electrode layer. The dielectric properties of the dielectric layer after adopting the supercritical fluids treatment have been significantly improved. While the hysteresis effect of the dielectric layers in the OFET devices has been basically eliminated, the sub-threshold slope of the OFET is also significantly reduced, the carrier mobility is effectively improved. Additionally, an OFET switching rate after being processed is improved, and, by connecting the LEDs in series, the switching rate of the LED is increased.

Abstract: A method and a system for recommending a target garment matching an inputted garment. The method includes: extracting attributes from text description and image of the inputted garment to obtain extracted attributes; querying a knowledge graph using the extracted attributes to obtain matched attributes; retrieving candidate products from a garment pool using the matched attributes; extracting features from the inputted garment and the candidate products; determining the target garment from the candidate products based on grading scores between the features of the inputted garment and the features of the candidate products; and recommending the target garment. The knowledge graph includes nodes corresponding to type of clothes, category of clothes, attribute keys, values of attribute keys, context keys, values of context keys, combination of the values of the attribute keys and the type of clothes, and combination of the value of the attribute keys and the category of clothes.

Abstract: Provided are a layered oxide and a preparation method thereof, a positive electrode sheet, a secondary battery, a battery module, a battery pack and an electrical apparatus. The layered oxide includes an oxide with the general formula NaxMnyAaQbCcO2, where A is one or two of Fe and Ni; Q is one or more of transition metal elements containing 3d or 4d orbital electrons except Fe and Ni; C is one or two of Al and B, 0.66<x?1, 0.2?y?0.6, 0.3?a?0.6, 0<b?0.2, 0<c?0.1, and 1?b/c?100. The A element undergoes valence changes to provide charge compensation in a charge and discharge process, thereby improving the specific capacity of the layered oxide; the Q element and oxygen form a hybrid orbital, inhibiting irreversible oxygen losses and structure collapse of oxygen under a high voltage; the C element has a high ionic potential so as to effectively inhibit oxygen losses; and 1?b/c?100.

Abstract: A human GLP-1 polypeptide variant, and a fusion protein or an immunoconjugate constructed by means of using the human GLP-1 polypeptide variant can be used for preventing, and/or treating metabolic diseases or conditions related to GLP-1.

Abstract: The present disclosure discloses an optical imaging system including, sequentially from an object side to an image side along an optical axis, a first lens having refractive power; a second lens having negative refractive power; a third lens having negative refractive power; a fourth lens having refractive power, a convex object-side surface and a concave image-side surface; and a fifth lens having refractive power. A distance TTL along the optical axis from an object-side surface of the first lens to an imaging plane of the optical imaging system and half of a diagonal length ImgH of an effective pixel area on the imaging plane of the optical imaging system satisfy: 1.0<TTL/ImgH<1.5.

Abstract: Provided are a positive active material for use in a sodium-ion battery, a method for preparing same, a positive electrode plate containing same, a sodium-ion battery, and an electrical device. The method for preparing a positive active material for use in a sodium-ion battery includes the following steps: mixing a positive active material for use in a sodium-ion battery with, and causing the positive active material to react with, a washing solution at a temperature of T1, and filtering and drying a product of the reaction to obtain a washed positive active material for use in a sodium-ion battery, where the washing solution is deionized water or an acidic solution with a pH value lower than 7.0, and 0° C.?T1<20° C.

Abstract: This application describes systems and methods for facilitating memory access for graph neural network (GNN) processing. An example method includes fetching, by an access engine circuitry implemented on a circuitry board, a portion of structure data of a graph from a pinned memory in a host memory of a host via a first peripheral component interconnect express (PCIe) connection; performing node sampling using the fetched portion of the structure data of the graph to select one or more sampled nodes; fetching, by the access engine circuitry, a portion of attribute data of the graph from the pinned memory via the first PCIe connection; sending the fetched portion of the attribute data of the graph to one or more processors; and performing, by the one or more processors, GNN processing for the graph using the fetched portion of the attribute data of the graph.

Abstract: The total memory space that is logically available to a processor in a general-purpose graphics processing unit (GPGPU) module is increased to accommodate terabyte-sized amounts of data by utilizing the memory space in an external memory module, and by further utilizing a portion of the memory space in a number of other external memory modules.

Abstract: A number of domain specific accelerators (DSA1-DSAn) are integrated into a conventional processing system (100) to operate on the same chip by adding additional instructions to a conventional instruction set architecture (ISA), and further adding an accelerator interface unit (130) to the processing system (100) to respond to the additional instructions and interact with the DSAs.

Abstract: An input weight pattern of a machine learning model may be received. The input weight pattern may be pruned to produce an output weight pattern based on a predetermined pruning algorithm. The pruning algorithm may include partitioning the input weight pattern into a plurality of sub-patterns, each row of the input weight pattern including sub-rows of a first number of sub-patterns, and each column of the input weight pattern including sub-columns of a second number of sub-patterns; and pruning sub-columns and sub-rows from the plurality of sub-patterns to achieve predetermined column and row sparsities respectively, with a constraint that at least one sub-row in each row of the input weight pattern is not pruned. The output weight pattern may further be compressed to produce a compact weight pattern. The compact weight pattern has lower memory and computational overheads as compared to the input weight pattern for the machine learning model.

Abstract: Aspects of the present technology are directed toward three-dimensional (3D) stacked processing systems characterized by high memory capacity, high memory bandwidth, low power consumption and small form factor. The 3D stacked processing systems include a plurality of processor chiplets and input/output circuits directly coupled to each of the plurality of processor chiplets.

Abstract: A layered-oxide positive electrode active material may have a molecular formula of NaxMnaFebNicMdNeO2-?Qf, where a doping element M is selected from at least one of Cu, Li, Ti, Zr, K, Sb, Nb, Mg, Ca, Mo, Zn, Cr, W, Bi, Sn, Ge, or Al, a doping element N is selected from at least one of Si, P, B, S, or Se, a doping element Q is selected from at least one of F, Cl, or N, 0.66?x?1, 0<a?0.70, 0<b?0.70, 0<c?0.23, 0?d<0.30, 0?e?0.30, 0?f?0.30, 0???0.30, a+b+c+d+e=1, 0<e+f?0.30, 0<(e+f)/a?0.30, 0.20?d+e+f?0.30, and (b+c)/a?1.5.

Abstract: A system-in-package architecture in accordance with aspects includes a logic die and one or more memory dice coupled together in a three-dimensional slack. The logic die can include one or more global building blocks and a plurality of local building blocks. The number of local building blocks can be scalable. The local building blocks can include a plurality of engines and memory controllers. The memory controllers can be configured to directly couple one or more of the engines to the one or more memory dice. The number and type of local building blocks, and the number and types of engines and memory controllers can be scalable.

Abstract: The present disclosure discloses an imaging lens assembly. Sequentially from an object side to an image side along an optical axis, the imaging lens assembly includes a first lens having a positive refractive power; a second lens having a negative refractive power, and both an object-side surface and an image-side surface thereof being concave surfaces; a third lens having a positive refractive power, and an image-side surface thereof being a convex surface; a fourth lens having a negative refractive power, and an object-side surface thereof being a concave surface; a fifth lens having a refractive power; and a sixth lens having a refractive power. A total effective focal length f of the imaging lens assembly and half of a diagonal length ImgH of an effective pixel area on an imaging plane of the imaging lens assembly satisfy 2.0?f/ImgH?3.0.

Abstract: The present disclosure discloses a camera lens assembly including, sequentially from an object side to an image side along an optical axis, a first lens, a second lens, a third lens, a fourth lens, a fifth lens and a sixth lens. The first lens has a positive refractive power; the second lens has a positive refractive power; the third lens has a refractive power; the fourth lens has a refractive power and an object-side surface thereof is a convex surface; the fifth lens has a positive refractive power; and the sixth lens has a negative refractive power. Half of a diagonal length ImgH of an effective pixel area on an imaging plane of the camera lens assembly and a total effective focal length f of the camera lens assembly satisfy 0.4<ImgH/f<0.6.

Abstract: The total memory space that is logically available to a processor in a general-purpose graphics processing unit (GPGPU) module is increased to accommodate terabyte-sized amounts of data by utilizing the memory space in an external memory module, and by further utilizing a portion of the memory space in a number of other external memory modules.

Abstract: The maximum capacity of a very fast memory in a system that requires very fast memory access times is increased by adding a memory with remote access times that are slower than required, and then moving infrequently accessed data from the memory with the very fast access times to the memory with the slow access times.

Abstract: A dual-model memory interface of a computing system is provided, configurable to present memory interfaces having differently-graded bandwidth capacity to different processors of the computing system. A mode switch controller of the memory interface controller, based on at least an arbitration rule written to a configuration register, switches the memory interface controller between a narrow-band mode and a wide-band mode. In each mode, the memory interface controller disables either a plurality of narrow-band memory interfaces of the memory interface controller according to a first bus standard, or a wide-band memory interface of the memory interface controller according to a second bus standard. The memory interface controller virtualizes a plurality of system memory units of the computing system as a virtual wide-band memory unit according to the second bus standard, or virtualizes a system memory unit of the computing system as a virtual narrow-band memory unit according to the first bus standard.