Abstract: A layered-oxide positive electrode active material may have a molecular formula of NaxMnaFebNicMdNeO2-?Qf, where a doping element M is selected from at least one of Cu, Li, Ti, Zr, K, Sb, Nb, Mg, Ca, Mo, Zn, Cr, W, Bi, Sn, Ge, or Al, a doping element N is selected from at least one of Si, P, B, S, or Se, a doping element Q is selected from at least one of F, Cl, or N, 0.66?x?1, 0<a?0.70, 0<b?0.70, 0<c?0.23, 0?d<0.30, 0?e?0.30, 0?f?0.30, 0???0.30, a+b+c+d+e=1, 0<e+f?0.30, 0<(e+f)/a?0.30, 0.20?d+e+f?0.30, and (b+c)/a?1.5.

Abstract: A system-in-package architecture in accordance with aspects includes a logic die and one or more memory dice coupled together in a three-dimensional slack. The logic die can include one or more global building blocks and a plurality of local building blocks. The number of local building blocks can be scalable. The local building blocks can include a plurality of engines and memory controllers. The memory controllers can be configured to directly couple one or more of the engines to the one or more memory dice. The number and type of local building blocks, and the number and types of engines and memory controllers can be scalable.

Abstract: The present disclosure discloses an imaging lens assembly. Sequentially from an object side to an image side along an optical axis, the imaging lens assembly includes a first lens having a positive refractive power; a second lens having a negative refractive power, and both an object-side surface and an image-side surface thereof being concave surfaces; a third lens having a positive refractive power, and an image-side surface thereof being a convex surface; a fourth lens having a negative refractive power, and an object-side surface thereof being a concave surface; a fifth lens having a refractive power; and a sixth lens having a refractive power. A total effective focal length f of the imaging lens assembly and half of a diagonal length ImgH of an effective pixel area on an imaging plane of the imaging lens assembly satisfy 2.0?f/ImgH?3.0.

Abstract: The present disclosure discloses a camera lens assembly including, sequentially from an object side to an image side along an optical axis, a first lens, a second lens, a third lens, a fourth lens, a fifth lens and a sixth lens. The first lens has a positive refractive power; the second lens has a positive refractive power; the third lens has a refractive power; the fourth lens has a refractive power and an object-side surface thereof is a convex surface; the fifth lens has a positive refractive power; and the sixth lens has a negative refractive power. Half of a diagonal length ImgH of an effective pixel area on an imaging plane of the camera lens assembly and a total effective focal length f of the camera lens assembly satisfy 0.4<ImgH/f<0.6.

Abstract: The total memory space that is logically available to a processor in a general-purpose graphics processing unit (GPGPU) module is increased to accommodate terabyte-sized amounts of data by utilizing the memory space in an external memory module, and by further utilizing a portion of the memory space in a number of other external memory modules.

Abstract: The maximum capacity of a very fast memory in a system that requires very fast memory access times is increased by adding a memory with remote access times that are slower than required, and then moving infrequently accessed data from the memory with the very fast access times to the memory with the slow access times.

Abstract: A dual-model memory interface of a computing system is provided, configurable to present memory interfaces having differently-graded bandwidth capacity to different processors of the computing system. A mode switch controller of the memory interface controller, based on at least an arbitration rule written to a configuration register, switches the memory interface controller between a narrow-band mode and a wide-band mode. In each mode, the memory interface controller disables either a plurality of narrow-band memory interfaces of the memory interface controller according to a first bus standard, or a wide-band memory interface of the memory interface controller according to a second bus standard. The memory interface controller virtualizes a plurality of system memory units of the computing system as a virtual wide-band memory unit according to the second bus standard, or virtualizes a system memory unit of the computing system as a virtual narrow-band memory unit according to the first bus standard.

Abstract: The present disclosure relates to a computer-implemented method for processing video data. The method comprises receiving a user input corresponding to a first picture of the video data, generating, based on the user input, prediction information of the first picture with respect a reference picture of the video data, and encoding the first picture using the prediction information.

Abstract: The present disclosure relates to an accelerator for systolic array-friendly data placement. The accelerator may include: a systolic array comprising a plurality of operation units, wherein the systolic array is configured to receive staged input data and perform operations using the staged input to generate staged output data, the staged output data comprising a number of segments; a controller configured to execute one or more instructions to generate a pattern generation signal; a data mask generator; and a memory configured to store the staged output data using the generated masks. The data mask generator may include circuitry configured to: receive the pattern generation signal from the controller, and, based on the received signal, generate a mask corresponding to each segment of the staged output data.

Abstract: The presented systems enable efficient and effective network communications. The presented systems enable efficient and effective network communications. In one embodiment a memory device includes a memory module, including a plurality of memory chips configured to store information; and an inter-chip network (ICN)/shared smart memory extension (SMX) memory interface controller (ICN/SMX memory interface controller) configured to interface between the memory module and an inter-chip network (ICN), wherein the ICN is configured to communicatively couple the memory device to a parallel processing unit (PPU). In one exemplary implementation, the ICN/SMX memory controller includes a plurality of package buffers, an ICN physical layer interface, a PRC/MAC interface, and a switch. The memory device and be a memory card including memory module (e.g., DDR DIMM, etc.).

Abstract: A chip or integrated circuit includes a layer that includes a first device and a second device. A scribe line is located between the first device and the second device and separates the first device from the second device. An electrically conductive connection traverses the scribe line and is coupled to the first device and the second device, thus connecting the first and second devices.

Abstract: The present disclosure relates to a method for controlling execution of a GEMM operation on an accelerator comprising multiple computation units, a first memory device, and a second memory device. The method comprises determining an execution manner of the GEMM operation, the execution manner comprising partition information of the GEMM operation and computation unit allocation information of the partitioned GEMM operation; generating one or more instructions to compute the partitioned GEMM operation on one or more allocated computation units; and issuing the one or more instructions to at least one of a first queue and a second queue, which enables at least one of a first local controller and a second local controller to execute the one or more instructions, wherein the first local controller and the second local controller are configured to control data movement between the computation units, the first memory device, and the second memory device.

Abstract: A system for processing encoded image components for artificial intelligence tasks. The system can include one or more compute units, one or more controllers and memory. The one or more controllers can include one or more micro-op schedulers and one or more channel switches. The one or more compute units can be configured to process components of the transformed domain image data according to one or more micro-operations for an artificial intelligence task. The one or more channel switches can be configured to selectively control the transfer of the components of transformed domain image data to the one or more compute units based on one or more gating flags. The one or more channel switches can also be configured to selectively control generation of the one or more micro-operations by the one or more micro-op schedulers based on the one or more gating flags.

Abstract: The present disclosure discloses an optical imaging lens group, along an optical axis from an object side to an image side, sequentially includes: an autofocus assembly, a first lens, a second lens, a third lens, a fourth lens, and at least one subsequent lens, where, a radius of curvature of an image-side surface of the autofocus assembly is variable.

Abstract: The present disclosure provides an optical imaging lens assembly, along an optical axis from an object side to an image side, sequentially includes: a first lens having positive refractive power; an autofocus component; a second lens having a refractive power; a third lens having a refractive power; a fourth lens having a refractive power; and at least one subsequent lens having a refractive power. At least one surface from an object-side surface of the first lens to an image-side surface of the at least one subsequent lens is an aspheric surface; the first lens and the autofocus component are cemented together; and a radius of curvature of an image-side surface of the autofocus component is variable.

Abstract: An optical imaging lens assembly is provided, along an optical axis from an object side to an image side, sequentially includes: a first lens having refractive power; an autofocus assembly; a second lens having refractive power, and an image-side surface of the second lens being a concave surface; a third lens having refractive power, and an image-side surface of the third lens being a convex surface; a fourth lens having refractive power, an object-side surface of the fourth lens being a concave surface, and an image-side surface of the fourth lens being a convex surface; and at least one subsequent lens having refractive power. A radius of curvature of an object-side surface of the autofocus assembly being variable.

Abstract: An optical imaging lens group, along an optical axis from an object side to an image side, sequentially includes: an autofocus component, a first lens, a second lens, a third lens, a fourth lens, and at least one subsequent lens. A radius of curvature of an image-side surface of the autofocus component is variable; and there is an interval between each two adjacent lenses among the first lens to the at least one subsequent lens.

Abstract: A method of scheduling instructions in a processing system comprising a processing unit and one or more co-processors comprises dispatching a plurality of instructions from a master processor to a co-processor of the one or more co-processors, wherein each instruction of the plurality of instructions comprises one or more additional fields, wherein at least one field comprises grouping information operable to consolidate the plurality of instructions for decomposition, and wherein at least one field comprises control information. The method also comprises decomposing the plurality of instructions into a plurality of fine-grained instructions, wherein the control information comprises rules associated with decomposing the plurality of instructions into the plurality of fine-grained instructions. Further, the method comprises scheduling the plurality of fine-grained instructions to execute on the co-processor, wherein the scheduling is performed in a non-sequential order.

Abstract: Image data is accessed. The image data includes frequency domain components. A subset of the frequency domain components is selected based on the relative importance of the frequency domain components. Only the subset of the frequency domain components is provided to an accelerator that executes a neural network to perform an artificial intelligence task using the subset of frequency domain components.

Abstract: The systems and methods are configured to efficiently and effectively include processing capabilities in memory. In one embodiment, a processing in memory (PIM) chip a memory array, logic components, and an interconnection network. The memory array is configured to store information. In one exemplary implementation the memory array includes storage cells and array periphery components. The logic components can be configured to process information stored in the memory array. The interconnection network is configured to communicatively couple the logic components. The interconnection network can include interconnect wires, and a portion of the interconnect wires are located in a metal layer area that is located above the memory array.