Abstract: A method of performing out-of-order execution in a processing system comprising a processing unit and one or more accelerators comprises dispatching a plurality of coarse-grained instructions, each instruction extended to comprise one or more tags, wherein each tag comprises dependency information for the respective instruction expressed at a coarse-grained level. The method also comprises translating the plurality of coarse-grained instructions into a plurality of fine-grained instructions, wherein the dependency information is translated into dependencies expressed at a fine-grained level. Further, the method comprises resolving the dependencies at the fine-grained level and scheduling the plurality of fine-grained instructions for execution across the one or more accelerators in the processing system.

Abstract: The present disclosure relates to a method for controlling execution of a GEMM operation on an accelerator comprising multiple computation units, a first memory device, and a second memory device. The method comprises determining an execution manner of the GEMM operation, the execution manner comprising partition information of the GEMM operation and computation unit allocation information of the partitioned GEMM operation; generating one or more instructions to compute the partitioned GEMM operation on one or more allocated computation units; and issuing the one or more instructions to at least one of a first queue and a second queue, which enables at least one of a first local controller and a second local controller to execute the one or more instructions, wherein the first local controller and the second local controller are configured to control data movement between the computation units, the first memory device, and the second memory device.

Abstract: The present disclosure provides an accelerator for processing a vector or matrix operation. The accelerator comprises a vector processing unit comprising a plurality of computation units having circuitry configured to process a vector operation in parallel; a matrix multiplication unit comprising a first matrix multiplication operator, a second matrix multiplication operator, and an accumulator, the first matrix multiplication operator and the second matrix multiplication operator having circuitry configured to process a matrix operation and the accumulator having circuitry configured to accumulate output results of the first matrix multiplication operator and the second matrix multiplication operator; and a memory storing input data for the vector operation or the matrix operation and being configured to communicate with the vector processing unit and the matrix multiplication unit.

Abstract: A system for determining the importance of encoded image components for artificial intelligence tasks includes an image capture or storage unit, a processor and a communication interface. The processor can receive components of transformed domain image data from the one or more image capture or storage units across the communication interface. The processor can be configured to determine the relative importance of the components of the transformed domain image data for an artificial intelligence task.

Abstract: The present disclosure relates to an accelerator for systolic array-friendly data placement. The accelerator may include: a systolic array comprising a plurality of operation units, wherein the systolic array is configured to receive staged input data and perform operations using the staged input to generate staged output data, the staged output data comprising a number of segments; a controller configured to execute one or more instructions to generate a pattern generation signal; a data mask generator; and a memory configured to store the staged output data using the generated masks. The data mask generator may include circuitry configured to: receive the pattern generation signal from the controller, and, based on the received signal, generate a mask corresponding to each segment of the staged output data.

Abstract: A chip or integrated circuit includes a layer that includes a first device and a second device. A scribe line is located between the first device and the second device and separates the first device from the second device. An electrically conductive connection traverses the scribe line and is coupled to the first device and the second device, thus connecting the first and second devices.

Abstract: The present disclosure relates to systems and methods concerning a system including a host device and a convolutional neural network hardware accelerator. The hardware accelerator can be configured, at least in part by the host device, to generate activation data from spatial-domain input data and spatial-domain weight data using frequency-domain operations. The hardware accelerator can include one or more discrete Fourier transform units configured to generate a frequency-domain representation of the input data. The hardware accelerator can include a multiplication unit configured to generate a frequency-domain representation of the activation data by element-wise complex multiplication of the frequency-domain representation of the input data and a frequency-domain representation of the weight data.

Abstract: The present disclosure discloses an optical imaging system including, sequentially from an object side to an image side along an optical axis, a first lens having refractive power; a second lens having negative refractive power; a third lens having negative refractive power; a fourth lens having refractive power, a convex object-side surface and a concave image-side surface; and a fifth lens having refractive power. A distance TTL along the optical axis from an object-side surface of the first lens to an imaging plane of the optical imaging system and half of a diagonal length ImgH of an effective pixel area on the imaging plane of the optical imaging system satisfy: 1.0<TTL/ImgH<1.5.

Abstract: Methods and systems are provided for improving memory control. A memory architecture includes a plurality of memory units and an interface. A respective memory unit of the plurality of memory units is configured with a Processing-In-Memory (PIM) architecture. The interface includes a plurality of lines. The interface is coupled between the plurality of memory units and a host. The interface is configured to receive one or more signals from a host via the plurality of lines. The respective memory unit of the plurality of memory units is coupled with a respective line of the plurality of lines, and the respective memory unit is further configured to receive a respective signal of the one or more signals via the interface so as to be individually selected by the host.

Abstract: Embodiments of the disclosure provide methods and systems for processing a neural network associated with an input matrix having a first number of elements. The method can include: dividing the input matrix into a plurality of vectors, each vector having a second number of elements; grouping the plurality of vectors into a first group of vectors and a second group of vectors; and pruning the first group of vectors and the second group of vectors.

Abstract: Methods and systems are provided for improving memory control. A memory architecture includes a plurality of memory units and an interface. A respective memory unit of the plurality of memory units is configured with a Processing-In-Memory (PIM) architecture. The interface includes a plurality of lines. The interface is coupled between the plurality of memory units and a host. The interface is configured to receive one or more signals from a host via the plurality of lines. The respective memory unit of the plurality of memory units is coupled with a respective line of the plurality of lines, and the respective memory unit is further configured to receive a respective signal of the one or more signals via the interface so as to be individually selected by the host.

Abstract: Discrete cosine transformation (DCT) information can be estimated from adjacent blocks of the same frame. DCT information can be estimated from different frames. Motion vectors can be used to track the position of objects in some frames of the video. For example, a stream of encoded frames is received; the encoded frames are entropy decoded and dequantized to produce DCT information for blocks of the frames; and DCT information for a block in a frame is determined using the DCT information produced from the entropy decoding and dequantizing for a different block.

Abstract: A system for processing encoded image components for artificial intelligence tasks. The system can include one or more compute units, one or more controllers and memory. The one or more controllers can include one or more micro-op schedulers and one or more channel switches. The one or more compute units can be configured to process components of the transformed domain image data according to one or more micro-operations for an artificial intelligence task. The one or more channel switches can be configured to selectively control the transfer of the components of transformed domain image data to the one or more compute units based on one or more gating flags. The one or more channel switches can also be configured to selectively control generation of the one or more micro-operations by the one or more micro-op schedulers based on the one or more gating flags.

Abstract: Image data is accessed. The image data includes frequency domain components. A subset of the frequency domain components is selected based on the relative importance of the frequency domain components. Only the subset of the frequency domain components is provided to an accelerator that executes a neural network to perform an artificial intelligence task using the subset of frequency domain components.

Abstract: A system for determining the importance of encoded image components for artificial intelligence tasks includes an image capture or storage unit, a processor and a communication interface. The processor can receive components of transformed domain image data from the one or more image capture or storage units across the communication interface. The processor can be configured to determine the relative importance of the components of the transformed domain image data for an artificial intelligence task.

Abstract: An input weight pattern of a machine learning model may be received. The input weight pattern may be pruned to produce an output weight pattern based on a predetermined pruning algorithm. The pruning algorithm may include partitioning the input weight pattern into a plurality of sub-patterns, each row of the input weight pattern including sub-rows of a first number of sub-patterns, and each column of the input weight pattern including sub-columns of a second number of sub-patterns; and pruning sub-columns and sub-rows from the plurality of sub-patterns to achieve predetermined column and row sparsities respectively, with a constraint that at least one sub-row in each row of the input weight pattern is not pruned. The output weight pattern may further be compressed to produce a compact weight pattern. The compact weight pattern has lower memory and computational overheads as compared to the input weight pattern for the machine learning model.

Abstract: An optical imaging lens assembly includes a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens and a seventh lens, which have refractive power and are sequentially arranged from an object side to an image side of the optical imaging lens assembly along an optical axis. The first lens and the third lens both have positive refractive power. The fifth lens has negative refractive power. A total effective focal length f of the optical imaging lens assembly and an entrance pupil diameter EPD of the optical imaging lens assembly satisfy f/EPD<1.3.

Abstract: The present disclosure discloses a camera lens assembly including, sequentially from an object side to an image side along an optical axis, a first lens, a second lens, a third lens, a fourth lens, a fifth lens and a sixth lens. The first lens has a positive refractive power; the second lens has a positive refractive power; the third lens has a refractive power; the fourth lens has a refractive power and an object-side surface thereof is a convex surface; the fifth lens has a positive refractive power; and the sixth lens has a negative refractive power. Half of a diagonal length ImgH of an effective pixel area on an imaging plane of the camera lens assembly and a total effective focal length f of the camera lens assembly satisfy 0.4<ImgH/f<0.6.

Abstract: The present disclosure discloses an imaging lens assembly. Sequentially from an object side to an image side along an optical axis, the imaging lens assembly includes a first lens having a positive refractive power; a second lens having a negative refractive power, and both an object-side surface and an image-side surface thereof being concave surfaces; a third lens having a positive refractive power, and an image-side surface thereof being a convex surface; a fourth lens having a negative refractive power, and an object-side surface thereof being a concave surface; a fifth lens having a refractive power; and a sixth lens having a refractive power. A total effective focal length f of the imaging lens assembly and half of a diagonal length ImgH of an effective pixel area on an imaging plane of the imaging lens assembly satisfy 2.0?f/ImgH?3.0.

Abstract: Embodiments of the present disclosure provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of resistors in the RRAM crossbar array are all set to Ron or Roff to indicate a value 1 or 0. Based on the foregoing setting, an operation is implemented using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved.