Patents by Inventor Yuichi Matsuda

Yuichi Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070136422
    Abstract: Disclosed are a computer-readable recording medium which records communication programs, communication method and communication apparatus capable of easily performing selection and execution of communication units according to communication units of communication partners. A profile management unit manages specific information including a combination of device type information and user identification information in each communication unit, and user IDs associated with the combined information. An application controller, when a session using any one of communication units is established between users, refers to specific information and associates user IDs with the combined information in the communication unit. A collection unit collects presence information where state information indicating whether communication units are available is associated with the combined information in each communication unit.
    Type: Application
    Filed: July 19, 2006
    Publication date: June 14, 2007
    Inventors: Takeshi Ohtani, Yuichi Matsuda, Yutaka Iwayama
  • Publication number: 20050214559
    Abstract: An in-mold coating molded article is obtained by coating the surface of a resin molded product comprising a hydroxyl group-containing polypropylene resin composition (A) with a paint composition for in-mold coating, wherein the composition (A) comprises a polypropylene resin (i), an additive rubber (ii) and optionally a polymer compound (iii) other than the polypropylene resin (i) and the additive rubber (ii), the total hydroxyl value of the polypropylene resin (i), the additive rubber (ii) and the optional polymer compound (iii) is from 1 to 40, the composition (A) has a rubber component content (total of the amount of the additive rubber (ii) and the amount of components soluble in n-decane at 23° C.
    Type: Application
    Filed: August 21, 2003
    Publication date: September 29, 2005
    Inventors: Takeshi Minoda, Yuichi Matsuda, Kaoru Yorita, Kenji Yonemochi, Kenji Oota, Etsuo Okahara, Toshio Arai
  • Patent number: 6931724
    Abstract: A method of producing a multilayered substrate having: a first face being provided with pads bondable to electrode terminals of a semiconductor element, and a body containing a plurality of wiring line layers and insulation layers successively formed from the side of the multilayered substrate at which the face for mounting a semiconductor element is located, wherein the final insulating layer forms provides a second face of the multilayered substrate. The successive wiring line layers are connected by vias, and the second face has external connection terminal pads. The pads on the first face are formed on a metal sheet, a first layer of insulating material is formed on the metal sheet so as to cover the pads formed thereon, holes are formed through the insulating material to expose the end face of the pad, and a patterned metal layer is formed to provide a layer of wiring lines and vias connecting the pads with the wiring line on the layer of insulating material.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: August 23, 2005
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Akio Rokugawa, Masayuki Sasaki, Yuichi Matsuda
  • Publication number: 20050017271
    Abstract: A substrate of multilayered structure having a. plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.
    Type: Application
    Filed: August 18, 2004
    Publication date: January 27, 2005
    Inventors: Akio Rokugawa, Masayuki Sasaki, Yuichi Matsuda
  • Patent number: 6828669
    Abstract: An interconnection substrate comprises an uppermost interconnection layer having a plurality of terminal pads located at positions corresponding to a plurality of solder bumps (external connection terminals) provided on a semiconductor element which is to be mounted on the interconnection substrate. The interconnection substrate also has a metal column formed on each of the terminal pads and has a resin film covering a side surface of the metal column. The interconnection substrate further has an insulating layer formed on the uppermost interconnection layer so that a gap is formed between the insulating layer and an outer peripheral surface of the resin film.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: December 7, 2004
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Takahiro Iijima, Shinichi Wakabayashi, Yuichi Matsuda
  • Patent number: 6756430
    Abstract: A flame-retarding thermoplastic resin composition which is composed essentially of (A) a component of thermoplastic resin, (B) a component of nitrogen atom-containing phosphatic compound, (C) a component of hydroxyl group-containing compound or partly esterified product thereof and (D) a component of neutralizer for acids, with optional component (E) of triazine derivative or (F) of metal alkoxide, wherein the proportion of each component is such that the component (A) is in the range from 60 to 90 parts by weight, the sum of the components (B)+(C) is in the range from 10 to 40 parts by weight and the component (D) is in the range from 0.1 to 5 parts by weight, per 100 parts by weight of the total sum of (A)+(B)+(C), respectively, wherein the weight ratio of (B)/(C) amounts to at least 1.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: June 29, 2004
    Assignee: Mitsui Chemicals, Inc.
    Inventors: Yuichi Matsuda, Mikio Hashimoto, Ikunori Sakai
  • Publication number: 20020195272
    Abstract: A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.
    Type: Application
    Filed: July 30, 2002
    Publication date: December 26, 2002
    Applicant: Shinko Electric Industries Co., Ltd.
    Inventors: Akio Rokugawa, Masayuki Sasaki, Yuichi Matsuda
  • Patent number: 6441314
    Abstract: A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: August 27, 2002
    Assignee: Shinko Electric Industries Co., Inc.
    Inventors: Akio Rokugawa, Masayuki Sasaki, Yuichi Matsuda
  • Patent number: 6418615
    Abstract: A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: July 16, 2002
    Assignee: Shinko Electronics Industries, Co., Ltd.
    Inventors: Akio Rokugawa, Masayuki Sasaki, Yuichi Matsuda
  • Publication number: 20020013392
    Abstract: A flame-retarding thermoplastic resin composition which is composed essentially of
    Type: Application
    Filed: June 12, 2001
    Publication date: January 31, 2002
    Applicant: GRAND POLYMER CO., LTD.
    Inventors: Yuichi Matsuda, Mikio Hashimoto, Ikunori Sakai
  • Publication number: 20010013425
    Abstract: A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.
    Type: Application
    Filed: March 23, 2001
    Publication date: August 16, 2001
    Applicant: Shinko Electric Industries Co., Ltd.
    Inventors: Akio Rokugawa, Masayuki Sasaki, Yuichi Matsuda
  • Publication number: 20010008309
    Abstract: An interconnection substrate comprises an uppermost interconnection layer having a plurality of terminal pads located at positions corresponding to a plurality of solder bumps (external connection terminals) provided on a semiconductor element which is to be mounted on the interconnection substrate. The interconnection substrate also has a metal column formed on each of the terminal pads and has a resin film covering a side surface of the metal column. The interconnection substrate further has an insulating layer formed on the uppermost interconnection layer so that a gap is formed between the insulating layer and an outer peripheral surface of the resin film.
    Type: Application
    Filed: December 14, 2000
    Publication date: July 19, 2001
    Inventors: Takahiro Iijima, Shinichi Wakabayashi, Yuichi Matsuda
  • Patent number: 5636206
    Abstract: An alarm masking system is provided which is capable of implementing alarm priority processing or alarm inhibit processing in ATM transmission equipment. In ATM transmission equipment, a received virtual path or virtual channel is switched by means of a switching unit and then sent to an interface unit. In doing this, if a higher priority alarm is detected or received at a reception side interface unit, an intra-office tag is added to the alarm cell and then it is output, so that by detecting this intra-office tag it is possible to inhibit generation of lower priority alarms in response to the higher order alarm.
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: June 3, 1997
    Assignee: Fujitsu Limited
    Inventors: Shigeo Amemiya, Yuichi Matsuda, Takao Ogura, Yasuki Fujii, Koji Tezuka, Hiromi Ueda, Hitoshi Uematsu
  • Patent number: 5510515
    Abstract: The present invention provides a process for purifying a polar vinyl compound, comprising pressurizing a crude polar vinyl compound containing impurities such as polymerization inhibiting substances and components of starting materials used in preparation of the polar vinyl compound to 500-3000 atm at 0.degree.-100.degree. C., the polar vinyl compound having at least one member selected from among oxygen, nitrogen and sulfur atoms, to thereby form crystals of the polar vinyl compound and separating the crystals of the polar vinyl compound from a liquid phase under pressure.
    Type: Grant
    Filed: September 16, 1994
    Date of Patent: April 23, 1996
    Assignees: Showa Denko K.K., Kabushiki Kaisha Kobe Seiko Sho
    Inventors: Toshiyuki Akizawa, Hiroyuki Hasegawa, Hitoshi Nakamura, Katsufumi Urabe, Shingo Yoshida, Yuichi Matsuda, Tamiharu Sakai