Abstract: In order to reduce the possibility of erroneous switching of an operation mode, an oscillation circuit, an oscillator, an electronic device and a moving object including: a power source detecting section that detects a power supply state; a determining section that determines an input state of a predetermined signal; and a control section that switches a operation mode when the determining section determines that input of the predetermined signal is detected within a predetermined time after it is detected that power is supplied, and a control method of the oscillator are provided.

Abstract: A clock generating device measures a frequency ratio between a clock signal (32.768 kHz+?) and a reference frequency value based on a clock signal (25 MHz); generates a clock signal obtained by masking a portion of clocks of the clock signal based on a measurement result of the frequency ratio; and updates a compensation value of a frequency temperature characteristic of the clock signal when a difference between the measurement result of the frequency ratio and an average value of N (N is a natural number) measurement results is greater than a reference value of the frequency ratio.

Abstract: An oscillation circuit includes a voltage controlled oscillation circuit that includes a variable capacitance circuit provided with a variable capacitance element whose capacitance value is controlled on the basis of a control voltage and oscillates a vibrator so as to generate an oscillation signal, and a fractional N-PLL circuit that receives the oscillation signal generated by the voltage controlled oscillation circuit and includes a voltage controlled oscillator which controls an oscillation frequency on the basis of control input data (an integral division ratio and a fractional division ratio).

Abstract: In order to reduce the possibility of erroneous switching of an operation mode, an oscillation circuit, an oscillator, an electronic device and a moving object including: a power source detecting section that detects a power supply state; a determining section that determines an input state of a predetermined signal; and a control section that switches a operation mode when the determining section determines that input of the predetermined signal is detected within a predetermined time after it is detected that power is supplied, and a control method of the oscillator are provided.

Abstract: A clock generation device measures a frequency ratio between a clock signal CK1 (32.768 kHz+?) and a reference frequency value based on a clock signal CK3 (25 MHz), generates a clock signal CK2 obtained by masking at least one clock pulse of the clock signal CK1 based on the measurement result of the frequency ratio, and controls the measurement interval of the frequency ratio based on the difference between the measurement result of the frequency ratio and an average value of N (N is a natural number) measurement results of the frequency ratio.

Abstract: In order to configure an oscillation circuit, an oscillator, a fractional N-PLL circuit, and the like that can output a plurality of frequencies, while decreasing an influence of an integer value boundary spurious at one reference frequency, the oscillation circuit includes a circuit for oscillation that oscillates a resonator, a fractional N-PLL circuit to which a signal from the circuit for oscillation is input, and a non-volatile memory that stores a plurality of division ratios, which can be selected from outside, of the fractional N-PLL circuit. A fractional portion of at least two of the plurality of division ratios is equal to or higher than 0.05 and is equal to or lower than 0.95.

Abstract: An oscillation circuit includes a voltage controlled oscillation circuit that includes a variable capacitance circuit provided with a variable capacitance element whose capacitance value is controlled on the basis of a control voltage and oscillates a vibrator so as to generate an oscillation signal, and a fractional N-PLL circuit that receives the oscillation signal generated by the voltage controlled oscillation circuit and includes a voltage controlled oscillator which controls an oscillation frequency on the basis of control input data (an integral division ratio and a fractional division ratio).

Abstract: A clock generating device measures a frequency ratio between a clock signal (32.768 kHz+?) and a reference frequency value based on a clock signal (25 MHz); generates a clock signal obtained by masking a portion of clocks of the clock signal based on a measurement result of the frequency ratio; and updates a compensation value of a frequency temperature characteristic of the clock signal when a difference between the measurement result of the frequency ratio and an average value of N (N is a natural number) measurement results is greater than a reference value of the frequency ratio.

Abstract: A clock generation device measures a frequency ratio between a clock signal CK1 (32.768 kHz+?) and a reference frequency value based on a clock signal CK3 (25 MHz), generates a clock signal CK2 obtained by masking at least one clock pulse of the clock signal CK1 based on the measurement result of the frequency ratio, and controls the measurement interval of the frequency ratio based on the difference between the measurement result of the frequency ratio and an average value of N (N is a natural number) measurement results of the frequency ratio.

Abstract: An oscillation circuit, an oscillator, an electronic device, and a moving object which are capable of adjusting an output frequency in a high modulation bandwidth with a high level of accuracy and adjusting a timing at which the output frequency is changed are provided. The oscillation circuit generates an oscillation signal by oscillating an oscillation element and includes a communication unit that receives frequency setting data for setting a frequency of the oscillation signal and frequency change data which is given a timing at which the frequency of the oscillation signal is changed on the basis of the frequency setting data, by serial transfer, and registers in which the frequency setting data and the frequency change data received by the communication unit are stored, respectively. An address of the register storing the frequency setting data is continuous with an address of the register storing the frequency change data.

Abstract: An oscillation circuit, an oscillator, an electronic device and a moving object, having at least a serial interface and an output enabling function, which are capable of implementing the control of output enabling without performing exclusive switching control using a switch, are provided. The oscillation circuit generates an oscillation signal by oscillating an oscillation element, and includes a first terminal to which characteristic control data for controlling characteristics of the oscillation signal including at least a frequency is input and to which control data of a first output control signal for controlling an output of the oscillation signal is input.

Abstract: A clock generation device generates a clock signal which has a predetermined number of clocks for each predetermined time in such a way that a clock signal (32.768 kHz+? (? is zero or a positive number)) is input and some clocks of the clock signal are masked.

Abstract: A data driver includes a capture start timing setting register in which is set data for setting capture start timing of the gray-scale data based on a signal which indicates supply start timing of the gray-scale data, and a capture instruction signal generation circuit which generates first and second capture instruction signals which are delayed in relation to the signal which indicates the supply start timing of the gray-scale data for a period corresponding to the data set in the capture start timing setting register. First and second data latches capture gray-scale data on a gray-scale bus at timing based on the first and second capture instruction signals, respectively. First and second driver circuits drive comb-tooth distributed data lines belonging to first and second groups based on the gray-scale data captured in the first and second data latches, respectively.

Abstract: A data driver drives comb-tooth distributed data lines of an electro-optical device in units of a predetermined number of data lines. The data driver includes first and second divided gray-scale buses, a gray-scale bus to which gray-scale data is supplied corresponding to an arrangement order of each of the data lines, a gray-scale data distribution circuit which distributes and outputs the gray-scale data supplied to the gray-scale bus to the first and second divided gray-scale buses, a first driver circuit which drives the data lines belonging to a first group among the data lines based on the gray-scale data output to the first divided gray-scale bus by the gray-scale data distribution circuit, and a second driver circuit which drives the data lines belonging to a second group among the data lines based on the gray-scale data output to the second divided gray-scale bus by the gray-scale data distribution circuit.

Abstract: A decoder circuit comprises: first decoder section that decodes an m-bit address signal portion of an (m+n)-bit address signal; and a second decoder section that decodes an n-bit address signal portion of the (m+n)-bit address signal, the first decoder section including a first AND operation circuit section that outputs signals that indicate a decoding result of the m-bit address signal portion, and a second AND operation circuit section that outputs signals that indicate a decoding result of part of the m-bit address signal portion, and the second decoder section including a third AND operation circuit section that outputs signals that indicate a decoding result of the n-bit address signal portion, and a fourth AND operation circuit section that outputs signals that indicate a decoding result of part of the n-bit address signal portion.

Abstract: A display driver including a shift register which shifts a shift start signal based on a shift clock to output a shift output from flip-flops thereof; a shift register control circuit which controls the shift register; a data latch which fetches display data on a display data bus, based on the shift output of the shift register; and a drive circuit which drives data lines based on the display data that has been fetched into the data latch. The shift register control circuit supplies the shift clock to the shift register in a vertical scan period, to cause the shift register to fetch display data for one horizontal scan, then halts the supply of the shift clock, and also supplies the shift clock to the shift register in a vertical blanking period, to clear the contents held in the shift register.

Abstract: A decoder circuit comprises: first decoder section that decodes an m-bit address signal portion of an (m+n)-bit address signal; and a second decoder section that decodes an n-bit address signal portion of the (m+n)-bit address signal, the first decoder section including a first AND operation circuit section that outputs signals that indicate a decoding result of the m-bit address signal portion, and a second AND operation circuit section that outputs signals that indicate a decoding result of part of the m-bit address signal portion, and the second decoder section including a third AND operation circuit section that outputs signals that indicate a decoding result of the n-bit address signal portion, and a fourth AND operation circuit section that outputs signals that indicate a decoding result of part of the n-bit address signal portion.

Abstract: A method of driving an electro-optical device that drives a source line of the electro-optical device based on K-bit (K is an integer equal to or larger than two) grayscale data includes, when data of a most significant bit of the grayscale data is first data, generating converted grayscale data by converting data of lower-order (K-L) bits (K>L, L is a positive integer) of the grayscale data so that a code word distance between the data of the lower-order (K-L) bits of the grayscale data before conversion and the data of the lower-order (K-L) bits of the grayscale data after conversion is equal to or less than (K-L); and driving the source line based on a grayscale signal corresponding to the converted data in a first polarity drive period, and driving the source line based on a grayscale signal corresponding to data obtained by converting higher-order L bits of the converted data so that a code word distance between data of the higher-order L bits of the converted data before conversion and the data of th

Abstract: A display driver includes an instruction signal generation circuit which generates a data-fetch-start-instruction-signal; a data latch which fetches display data at data fetch timings including a fetch start timing that is determined by the data-fetch-start-instruction-signal; and a data line drive circuit which drives the data lines, based on the display data fetched into the data latch. The instruction signal generation circuit includes a fetch-start-timing-setting-register into which is set data for determining the fetch start timing of the display data, and the instruction signal generation circuit generates the data-fetch-start-instruction-signal that changes when a period corresponding to the data set in the fetch-start-timing-setting-register has elapsed, with reference to a reference timing.

Abstract: A display driver which drives a plurality of data lines of an electro-optical device includes a capture start timing setting register in which is set a period between a changing time of a given capture start timing instruction signal and a staring time of capturing the gray-scale data, and shift start signal generation circuit which generates a shift start signal based on a setting state of the capture start timing setting register. The display driver includes a shift register which shifts the shift start signal based on a given shift clock signal, and outputs a shift output, and a data latch which includes a plurality of flip-flops, each of which holds the gray-scale data based on the shift output from the shift register, and outputs a data signal corresponding to the gray-scale data held in the data latch to the data lines.