Abstract: A comb-tooth drive is realized by a display driver which drives data lines. The display driver includes a gray-scale bus to which gray-scale data is supplied corresponding to an arrangement order of the data lines, first and second bidirectional shift registers of which the shift directions are determined based on first and second shift direction control signals and which shift first and second shift start signals based on first and second shift clock signals, first and second data latches which latch the gray-scale data based on shift outputs, and a data line driver circuit which drives the data lines based on the latch data.

Abstract: A display driver multiplexes gray-scale data captured by a data latch and outputs a data signal to a comb-tooth distributed data line. The data latch includes a gray-scale bus to which the gray-scale data for first to third color components is supplied corresponding to the arrangement order of the data lines. A first data latch, a second data latch, a first shift register, a second shift register, a first clock signal line, and a second clock signal line are N multiplexed. A multiplexer multiplexes N sets of gray-scale data captured by the first and second data latches. The display driver outputs the data signal corresponding to first or second multiplexed data to a data signal supply line.

Abstract: A display driver includes an instruction signal generation circuit which generates a data-fetch-start-instruction-signal; a data latch which fetches display data at data fetch timings including a fetch start timing that is determined by the data-fetch-start-instruction-signal; and a data line drive circuit which drives the data lines, based on the display data fetched into the data latch. The instruction signal generation circuit includes a fetch-start-timing-setting-register into which is set data for determining the fetch start timing of the display data, and the instruction signal generation circuit generates the data-fetch-start-instruction-signal that changes when a period corresponding to the data set in the fetch-start-timing-setting-register has elapsed, with reference to a reference timing.

Abstract: A comb-tooth drive is realized by using a display driver which drives data lines. The display driver includes: a gray-scale bus to which gray-scale data is supplied corresponding to an arrangement order of each of the data lines; first and second clock lines to which first and second shift clocks are supplied; first and second shift registers which shift first and second shift start signals in first and second shift directions based on the first and second shift clocks, respectively; first and second data latches which latch the gray-scale data based on the shift outputs of the first and second shift registers, respectively; and a data line driver circuit which drives the data lines based on the data latched by the first and second data latches.

Abstract: A comb-tooth drive is realized by a display driver which drives data lines. The display driver includes a gray-scale bus to which gray-scale data is supplied corresponding to an arrangement order of the data lines, first and second clock lines to which a first or second shift clock is supplied, a first and second shift registers which shift signals in first and second shift directions based on first and second shift clocks, first and second data latches which latch the gray-scale data based on the shift output of the first and second shift registers, a data line driver circuit which drives the data lines based on latch data of each data latch, and a clock switch circuit which selectively outputs the first and second shift clocks based on a given mode setting signal.

Abstract: A display driver circuit includes first to Mth SR blocks which are disposed in a region on the right side of a data input control circuit and hold first to Mth gray-scale data, and (M+1)th to (M+N)th SR blocks which are disposed in a region on the left side of the data input control circuit and hold (M+1)th to (M+N)th gray-scale data. The first to (M+N)th SR blocks hold the first to (M+N)th gray-scale data for which mask control is performed based on a data enable signal shifted by each SR block. The first to Mth gray-scale data is masked in order from first to Mth data mask circuit. The (M+1)th to (M+N)th gray-scale data are unmasked in order from (M+1)th to (M+N)th data mask circuit.

Abstract: A display driver circuit holds a gray-scale value in a gray-scale value latch circuit corresponding to a shift output signal from a shift register, and drives first to Mth (M is an integer of two or more) signal electrodes. The gray-scale value latch circuit includes first to Mth gray-scale value latches. First to kth (1≦k<M, k is an integer) gray-scale value latches among the first to Mth gray-scale value latches take in the gray-scale value on a left gray-scale value signal bus based on the shift output signal. (k+1)th to Mth gray-scale value latches among the first to Mth gray-scale value latches take in the gray-scale value on a right gray-scale value signal bus based on the shift output signal. A bus dividing circuit outputs the gray-scale value on a gray-scale value bus to either or both of the left and right gray-scale value signal buses based on a bus dividing signal.