Abstract: A display driver multiplexes gray-scale data captured by a data latch and outputs a data signal to a comb-tooth distributed data line. The data latch includes a gray-scale bus to which the gray-scale data for first to third color components is supplied corresponding to the arrangement order of the data lines. A first data latch, a second data latch, a first shift register, a second shift register, a first clock signal line, and a second clock signal line are N multiplexed. A multiplexer multiplexes N sets of gray-scale data captured by the first and second data latches. The display driver outputs the data signal corresponding to first or second multiplexed data to a data signal supply line.

Abstract: A comb-tooth drive is realized by using a display driver which drives data lines. The display driver includes: a gray-scale bus to which gray-scale data is supplied corresponding to an arrangement order of each of the data lines; first and second clock lines to which first and second shift clocks are supplied; first and second shift registers which shift first and second shift start signals in first and second shift directions based on the first and second shift clocks, respectively; first and second data latches which latch the gray-scale data based on the shift outputs of the first and second shift registers, respectively; and a data line driver circuit which drives the data lines based on the data latched by the first and second data latches.

Abstract: A display driver circuit includes first to Mth SR blocks which are disposed in a region on the right side of a data input control circuit and hold first to Mth gray-scale data, and (M+1)th to (M+N)th SR blocks which are disposed in a region on the left side of the data input control circuit and hold (M+1)th to (M+N)th gray-scale data. The first to (M+N)th SR blocks hold the first to (M+N)th gray-scale data for which mask control is performed based on a data enable signal shifted by each SR block. The first to Mth gray-scale data is masked in order from first to Mth data mask circuit. The (M+1)th to (M+N)th gray-scale data are unmasked in order from (M+1)th to (M+N)th data mask circuit.

Abstract: A display driver circuit includes first to Mth SR blocks which are disposed in a region on the right side of a data input control circuit and hold first to Mth gray-scale data, and (M+1)th to (M+N)th SR blocks which are disposed in a region on the left side of the data input control circuit and hold (M+1)th to (M+N)th gray-scale data. The first to (M+N)th SR blocks hold the first to (M+N)th gray-scale data for which mask control is performed based on a data enable signal shifted by each SR block. The first to Mth gray-scale data is masked in order from first to Mth data mask circuit. The (M+1)th to (M+N)th gray-scale data are unmasked in order from (M+1)th to (M+N)th data mask circuit.

Abstract: A display driver includes a front drawing row designation register, a partial mode setting register, a data line driver circuit having an operational amplifier section and a partial non-display voltage output section, and a partial display control section. The front drawing row designation register is a register for designating one of the scanning lines corresponding to a front drawing row. The partial mode setting register is a register which sets for the scanning lines either a normal display mode in which a drive voltage depending on gray-scale data is supplied to at least one of the data lines, or a partial non-display mode in which a partial non-display voltage is supplied to at least one of the data lines. The operational amplifier section drives at least one of the data lines based on the drive voltage. The partial non-display voltage output section drives at least one of the data lines based on the partial non-display voltage. The partial display control section controls the data line driver circuit.

Abstract: A data driver drives comb-tooth distributed data lines of an electro-optical device in units of a predetermined number of data lines. The data driver includes first and second divided gray-scale buses, a gray-scale bus to which gray-scale data is supplied corresponding to an arrangement order of each of the data lines, a gray-scale data distribution circuit which distributes and outputs the gray-scale data supplied to the gray-scale bus to the first and second divided gray-scale buses, a first driver circuit which drives the data lines belonging to a first group among the data lines based on the gray-scale data output to the first divided gray-scale bus by the gray-scale data distribution circuit, and a second driver circuit which drives the data lines belonging to a second group among the data lines based on the gray-scale data output to the second divided gray-scale bus by the gray-scale data distribution circuit.

Abstract: A data driver includes a capture start timing setting register in which is set data for setting capture start timing of the gray-scale data based on a signal which indicates supply start timing of the gray-scale data, and a capture instruction signal generation circuit which generates first and second capture instruction signals which are delayed in relation to the signal which indicates the supply start timing of the gray-scale data for a period corresponding to the data set in the capture start timing setting register. First and second data latches capture gray-scale data on a gray-scale bus at timing based on the first and second capture instruction signals, respectively. First and second driver circuits drive comb-tooth distributed data lines belonging to first and second groups based on the gray-scale data captured in the first and second data latches, respectively.

Abstract: A display driver circuit includes first to Mth SR blocks which are disposed in a region on the right side of a data input control circuit and hold first to Mth gray-scale data, and (M+1)th to (M+N)th SR blocks which are disposed in a region on the left side of the data input control circuit and hold (M+1)th to (M+N)th gray-scale data. The first to (M+N)th SR blocks hold the first to (M+N)th gray-scale data for which mask control is performed based on a data enable signal shifted by each SR block. The first to Mth gray-scale data is masked in order from first to Mth data mask circuit. The (M+1)th to (M+N)th gray-scale data are unmasked in order from (M+1)th to (M+N)th data mask circuit.

Abstract: A data driver includes a capture start timing setting register in which is set data for setting capture start timing of the gray-scale data based on a signal which indicates supply start timing of the gray-scale data, and a capture instruction signal generation circuit which generates first and second capture instruction signals which are delayed in relation to the signal which indicates the supply start timing of the gray-scale data for a period corresponding to the data set in the capture start timing setting register. First and second data latches capture gray-scale data on a gray-scale bus at timing based on the first and second capture instruction signals, respectively. First and second driver circuits drive comb-tooth distributed data lines belonging to first and second groups based on the gray-scale data captured in the first and second data latches, respectively.

Abstract: A data driver drives comb-tooth distributed data lines of an electro-optical device in units of a predetermined number of data lines. The data driver includes first and second divided gray-scale buses, a gray-scale bus to which gray-scale data is supplied corresponding to an arrangement order of each of the data lines, a gray-scale data distribution circuit which distributes and outputs the gray-scale data supplied to the gray-scale bus to the first and second divided gray-scale buses, a first driver circuit which drives the data lines belonging to a first group among the data lines based on the gray-scale data output to the first divided gray-scale bus by the gray-scale data distribution circuit, and a second driver circuit which drives the data lines belonging to a second group among the data lines based on the gray-scale data output to the second divided gray-scale bus by the gray-scale data distribution circuit.

Abstract: A comb-tooth drive is realized by a display driver which drives data lines. The display driver includes a gray-scale bus to which gray-scale data is supplied corresponding to an arrangement order of the data lines, first and second clock lines to which a first or second shift clock is supplied, a first and second shift registers which shift signals in first and second shift directions based on first and second shift clocks, first and second data latches which latch the gray-scale data based on the shift output of the first and second shift registers, a data line driver circuit which drives the data lines based on latch data of each data latch, and a clock switch circuit which selectively outputs the first and second shift clocks based on a given mode setting signal.

Abstract: A display driver driving data lines and implementing comb-tooth drive. The display driver includes: a grayscale bus to which grayscale data is supplied corresponding to the arrangement order of the data lines; first and second bidirectional shift registers which output shift outputs of which shift directions are specified by first and second shift direction control signals; first and second data latches which latch the grayscale data based on the shift outputs; and a data line driver circuit which drives the data lines based on the latch data. The first and second shift direction control signals are output by first and second shift start signal switch circuits corresponding to the content of a drive mode setting register.

Abstract: A comb-tooth drive is realized by a display driver which drives data lines. The display driver includes a gray-scale bus to which gray-scale data is supplied corresponding to an arrangement order of the data lines, first and second bidirectional shift registers of which the shift directions are determined based on first and second shift direction control signals and which shift first and second shift start signals based on first and second shift clock signals, first and second data latches which latch the gray-scale data based on shift outputs, and a data line driver circuit which drives the data lines based on the latch data.

Abstract: A display driver circuit holds a gray-scale value in a gray-scale value latch circuit corresponding to a shift output signal from a shift register, and drives first to Mth (M is an integer of two or more) signal electrodes. The gray-scale value latch circuit includes first to Mth gray-scale value latches. First to kth (1?k<M, k is an integer) gray-scale value latches among the first to Mth gray-scale value latches take in the gray-scale value on a left gray-scale value signal bus based on the shift output signal. (k+1)th to Mth gray-scale value latches among the first to Mth gray-scale value latches take in the gray-scale value on a right gray-scale value signal bus based on the shift output signal. A bus dividing circuit outputs the gray-scale value on a gray-scale value bus to either or both of the left and right gray-scale value signal buses based on a bus dividing signal.

Abstract: A display driver including a shift register which shifts a shift start signal based on a shift clock to output a shift output from flip-flops thereof; a shift register control circuit which controls the shift register; a data latch which fetches display data on a display data bus, based on the shift output of the shift register; and a drive circuit which drives data lines based on the display data that has been fetched into the data latch. The shift register control circuit supplies the shift clock to the shift register in a vertical scan period, to cause the shift register to fetch display data for one horizontal scan, then halts the supply of the shift clock, and also supplies the shift clock to the shift register in a vertical blanking period, to clear the contents held in the shift register.

Abstract: A data driver includes a capture start timing setting register in which is set data for setting capture start timing of the gray-scale data based on a signal which indicates supply start timing of the gray-scale data, and a capture instruction signal generation circuit which generates first and second capture instruction signals which are delayed in relation to the signal which indicates the supply start timing of the gray-scale data for a period corresponding to the data set in the capture start timing setting register. First and second data latches capture gray-scale data on a gray-scale bus at timing based on the first and second capture instruction signals, respectively. First and second driver circuits drive comb-tooth distributed data lines belonging to first and second groups based on the gray-scale data captured in the first and second data latches, respectively.

Abstract: A data driver drives comb-tooth distributed data lines of an electro-optical device in units of a predetermined number of data lines. The data driver includes first and second divided gray-scale buses, a gray-scale bus to which gray-scale data is supplied corresponding to an arrangement order of each of the data lines, a gray-scale data distribution circuit which distributes and outputs the gray-scale data supplied to the gray-scale bus to the first and second divided gray-scale buses, a first driver circuit which drives the data lines belonging to a first group among the data lines based on the gray-scale data output to the first divided gray-scale bus by the gray-scale data distribution circuit, and a second driver circuit which drives the data lines belonging to a second group among the data lines based on the gray-scale data output to the second divided gray-scale bus by the gray-scale data distribution circuit.

Abstract: A display driver which drives a plurality of data lines of an electro-optical device includes a capture start timing setting register in which is set a period between a changing time of a given capture start timing instruction signal and a staring time of capturing the gray-scale data, and shift start signal generation circuit which generates a shift start signal based on a setting state of the capture start timing setting register. The display driver includes a shift register which shifts the shift start signal based on a given shift clock signal, and outputs a shift output, and a data latch which includes a plurality of flip-flops, each of which holds the gray-scale data based on the shift output from the shift register, and outputs a data signal corresponding to the gray-scale data held in the data latch to the data lines.

Abstract: A display driver driving data lines and implementing comb-tooth drive. The display driver includes: a grayscale bus to which grayscale data is supplied corresponding to the arrangement order of the data lines; first and second bidirectional shift registers which output shift outputs of which shift directions are specified by first and second shift direction control signals; first and second data latches which latch the grayscale data based on the shift outputs; and a data line driver circuit which drives the data lines based on the latch data. The first and second shift direction control signals are output by first and second shift start signal switch circuits corresponding to the content of a drive mode setting register.

Abstract: A display driver includes a front drawing row designation register, a partial mode setting register, a data line driver circuit having an operational amplifier section and a partial non-display voltage output section, and a partial display control section. The front drawing row designation register is a register for designating one of the scanning lines corresponding to a front drawing row. The partial mode setting register is a register which sets for the scanning lines either a normal display mode in which a drive voltage depending on gray-scale data is supplied to at least one of the data lines, or a partial non-display mode in which a partial non-display voltage is supplied to at least one of the data lines. The operational amplifier section drives at least one of the data lines based on the drive voltage. The partial non-display voltage output section drives at least one of the data lines based on the partial non-display voltage. The partial display control section controls the data line driver circuit.