Patents by Inventor Yuichiro Sasaki
Yuichiro Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153663Abstract: A radionuclide production system is a system for producing a radionuclide by irradiating a liquid containing a raw material nuclide with bremsstrahlung radiation, the radionuclide production system including: a circulation path configured to allow a liquid containing a raw material nuclide to circulate; and a radiation generation unit configured to generate bremsstrahlung radiation to irradiate the liquid. A metal member containing a pure metal of a platinum group or an alloy of the platinum group is provided at an upper portion in the circulation path. In a radionuclide production method, the raw material nuclide contained in the liquid is transformed to the radionuclide by irradiating the liquid with the bremsstrahlung radiation while circulating the liquid containing the raw material nuclide in the circulation path, and oxygen and hydrogen generated due to radiolysis of the liquid are removed by a recombination reaction with a metal member formed of the pure metal.Type: ApplicationFiled: March 17, 2022Publication date: May 9, 2024Inventors: Takahiro TADOKORO, Yuichiro UENO, Yuuko KANI, Kento NISHIDA, Takahiro WATANABE, Takahiro SASAKI, Masaharu ITO
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Publication number: 20240126516Abstract: A host computer is programmed to receive input specifying definitions of two or more stages, each of the stages representing an attribute of one or more end-user profiles that have undertaken one or more interactions, using computing devices associated with the end-user profiles, with one or more networked computers. For each stage, the user computer can interoperate with a graphical user interface comprising a virtual canvas, a palette comprising a plurality of different graphical icons each representing at least an entry condition and an activation order for digital presentation of information. Visual selection and dragging operations can move copies of an entry condition icon and an activation icon from the palette to the virtual canvas. An entry condition icon is defined using rules to match one or more subsets of the end-user profiles and one or more subsets of the interactions. An activation icon has order attributes order for the digital presentation of information.Type: ApplicationFiled: June 29, 2023Publication date: April 18, 2024Inventors: Yili Huang, Alexis Jianghezi Zheng, Nick Kobayashi, Reeba Benzialex, Kai Sasaki, Yuichiro Kaneko
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Publication number: 20240084893Abstract: A power generation system includes: a prime mover; a magnetic gear generator configured to be driven by an input from the prime mover to generate power; a power converter connected to the magnetic gear generator; an operation mode switch unit configured to switch an operation mode of the magnetic gear generator to a step-out avoidance mode in response to that a step-out parameter indicating a risk of step-out of the magnetic gear generator exceeds a prescribed allowable range; and a reduction command unit configured to give the prime mover an input reduction command to reduce the input from the prime mover and configured to give the power converter a torque reduction command to reduce a generator torque of the magnetic gear generator, in the step-out avoidance mode.Type: ApplicationFiled: February 22, 2022Publication date: March 14, 2024Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Tsuyoshi Wakasa, Mikito Sasaki, Yuichiro Yazaki, Takatoshi Matsushita, Yoshiki Kato
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Patent number: 11901356Abstract: A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).Type: GrantFiled: March 12, 2020Date of Patent: February 13, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seungha Oh, Pil-Kyu Kang, Kughwan Kim, Weonhong Kim, Yuichiro Sasaki, Sang Woo Lee, Sungkeun Lim, Yongho Ha, Sangjin Hyun
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Publication number: 20230284373Abstract: In a circuit board, a printed board includes an insulating base and a plurality of conductors disposed in layers in the insulating base. The conductors include a signal line electrically connected to an electronic component; and a potential fixed layer fixed to a predetermined potential and arranged to face the signal line across the insulating base in a thickness direction of the printed board. The potential fixed layer has a facing surface facing the signal line, and is provided with a high magnetic film having a magnetic permeability higher than that of the at least one potential fixed layer on the facing surface. The high magnetic film is disposed to overlap the signal line in the thickness direction. The signal line includes a facing line that faces the high magnetic film across the insulating base in the thickness direction.Type: ApplicationFiled: February 10, 2023Publication date: September 7, 2023Inventors: ERIKO YAZU, RYOSUKE OMURA, KAZUKI TAKAHASHI, KENICHI TAKESHIMA, YUICHIRO SASAKI
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Patent number: 11728347Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.Type: GrantFiled: October 5, 2021Date of Patent: August 15, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Weonhong Kim, Pilkyu Kang, Yuichiro Sasaki, Sungkeun Lim, Yongho Ha, Sangjin Hyun, Kughwan Kim, Seungha Oh
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Patent number: 11610838Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.Type: GrantFiled: July 6, 2021Date of Patent: March 21, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Yuichiro Sasaki, Sungkeun Lim, Pil-Kyu Kang, Weonhong Kim, Seungha Oh, Yongho Ha, Sangjin Hyun
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Publication number: 20220340506Abstract: The present invention provides a method for producing 1,3-butadiene that is capable of suppressing generation of reaction by-products. The method includes: a step (A) of to obtain a produced gas containing 1,3-butadiene; a step (B) of cooling the produced gas; and a step (C) of separating the produced gas cooled in the step (B) into molecular oxygen and inert gases, and other gases containing 1,3-butadiene, by selective absorption into an absorption solvent. In the method, in the step (A), the raw material gas and a molecular oxygen-containing gas are supplied to a fixed-bed reactor with a composite oxide catalyst containing molybdenum and bismuth; the molar ratio of molecular oxygen to n-butene in the gases is 1.0 to 2.0; and the molar ratio of water vapor to n-butene in the gases supplied to the fixed-bed reactor is not more than 1.2.Type: ApplicationFiled: August 26, 2020Publication date: October 27, 2022Applicants: JSR Corporation, ENEOS CorporationInventors: Junjie WANG, Yuichiro SASAKI, Takashi MORI
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Publication number: 20220289646Abstract: The present invention has as its object the provision of a method for producing 1,3-butadiene capable of efficiently purifying an absorption solvent while a high productivity is assured. A method for producing 1,3-butadiene includes: a step (A) of obtaining a produced gas containing 1,3-butadiene; a step (B) of cooling the produced gas; a step (C) of separating the produced gas, which has been subjected to the step (B); a step (D1) of separating the absorption solvent, that has absorbed an absorption component comprising the other gases containing 1,3 -butadiene into an absorption solvent that does not substantially contain the absorption component and an absorption solvent that contains the absorption component; a step (D2) of separating the absorption solvent that contains the absorption component into an absorption solvent that contains a reaction by-product and a 1,3-butadiene liquid; and a step (E) of purifying the absorption solvent, that contains the reaction by-product.Type: ApplicationFiled: August 26, 2020Publication date: September 15, 2022Applicants: JSR Corporation, ENEOS CorporationInventors: Mayu SUGIMOTO, Yuichiro SASAKI
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Patent number: 11322494Abstract: A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.Type: GrantFiled: September 9, 2020Date of Patent: May 3, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyungin Choi, Taehyeon Kim, Hongshik Shin, Taegon Kim, Jaeyoung Park, Yuichiro Sasaki
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Publication number: 20220028895Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.Type: ApplicationFiled: October 5, 2021Publication date: January 27, 2022Inventors: Weonhong KIM, Pilkyu KANG, Yuichiro SASAKI, Sungkeun LIM, Yongho HA, Sangjin HYUN, Kughwan KIM, Seungha OH
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Patent number: 11230513Abstract: A process of producing 1,3-butadiene includes: a first step of obtaining gases containing 1,3-butadiene by an oxidative dehydrogenation reaction of a raw material gas with a molecular oxygen-containing gas in the presence of a metal oxide catalyst, the raw material gas containing 1-butene and 2-butene and having a proportion of 2-butene to a sum of 1-butene and 2-butene, which is defined as 100% by volume, being not less than 50% by volume; a second step of cooling the produced gases obtained in the first step; and a third step of separating the produced gases having undergone the second step into molecular oxygen and inert gases and other gases containing 1,3-butadiene by selective absorption to an absorbing solvent, wherein the concentration of methyl vinyl ketone in the produced gases having been cooled in the second step is 0% by volume or more and not more than 0.03% by volume.Type: GrantFiled: September 4, 2020Date of Patent: January 25, 2022Assignees: JSR Corporation, ENEOS CORPORATIONInventors: Mayu Sugimoto, Yuichiro Sasaki, Sosuke Higuchi, Nobuhiro Kimura
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Patent number: 11177286Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.Type: GrantFiled: March 3, 2020Date of Patent: November 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Weonhong Kim, Pilkyu Kang, Yuichiro Sasaki, Sungkeun Lim, Yongho Ha, Sangjin Hyun, Kughwan Kim, Seungha Oh
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Publication number: 20210335707Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.Type: ApplicationFiled: July 6, 2021Publication date: October 28, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Yuichiro SASAKI, Sungkeun LIM, Pil-Kyu KANG, Weonhong KIM, Seungha OH, Yongho HA, Sangjin HYUN
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Patent number: 11121080Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.Type: GrantFiled: March 5, 2020Date of Patent: September 14, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Yuichiro Sasaki, Sungkeun Lim, Pil-Kyu Kang, Weonhong Kim, Seungha Oh, Yongho Ha, Sangjin Hyun
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Publication number: 20210020628Abstract: A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).Type: ApplicationFiled: March 12, 2020Publication date: January 21, 2021Inventors: SEUNGHA OH, PIL-KYU KANG, KUGHWAN KIM, WEONHONG KIM, YUICHIRO SASAKI, SANG WOO LEE, SUNGKEUN LIM, YONGHO HA, SANGJIN HYUN
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Publication number: 20210013204Abstract: A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.Type: ApplicationFiled: September 9, 2020Publication date: January 14, 2021Inventors: KYUNGIN CHOI, Taehyeon KIM, HONGSHIK SHIN, TAEGON KIM, JAEYOUNG PARK, YUICHIRO SASAKI
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Publication number: 20200399191Abstract: A process of producing 1,3-butadiene includes: a first step of obtaining gases containing 1,3-butadiene by an oxidative dehydrogenation reaction of a raw material gas with a molecular oxygen-containing gas in the presence of a metal oxide catalyst, the raw material gas containing 1-butene and 2-butene and having a proportion of 2-butene to a sum of 1-butene and 2-butene, which is defined as 100% by volume, being not less than 50% by volume; a second step of cooling the produced gases obtained in the first step; and a third step of separating the produced gases having undergone the second step into molecular oxygen and inert gases and other gases containing 1,3-butadiene by selective absorption to an absorbing solvent, wherein the concentration of methyl vinyl ketone in the produced gases having been cooled in the second step is 0% by volume or more and not more than 0.03% by volume.Type: ApplicationFiled: September 4, 2020Publication date: December 24, 2020Applicants: JSR Corporation, ENEOS CORPORATIONInventors: Mayu SUGIMOTO, Yuichiro SASAKI, Sosuke HIGUCHI, Nobuhiro KIMURA
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Publication number: 20200373331Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.Type: ApplicationFiled: March 3, 2020Publication date: November 26, 2020Inventors: Weonhong KIM, Pilkyu KANG, Yuichiro SASAKI, Sungkeun LIM, Yongho HA, Sangjin HYUN, Kughwan KIM, Seungha OH
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Publication number: 20200365509Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.Type: ApplicationFiled: March 5, 2020Publication date: November 19, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Yuichiro Sasaki, Sungkeun Lim, Pil-Kyu Kang, Weonhong Kim, Seungha Oh, Yongho Ha, Sangjin Hyun