Patents by Inventor Yuichiro Sasaki

Yuichiro Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153663
    Abstract: A radionuclide production system is a system for producing a radionuclide by irradiating a liquid containing a raw material nuclide with bremsstrahlung radiation, the radionuclide production system including: a circulation path configured to allow a liquid containing a raw material nuclide to circulate; and a radiation generation unit configured to generate bremsstrahlung radiation to irradiate the liquid. A metal member containing a pure metal of a platinum group or an alloy of the platinum group is provided at an upper portion in the circulation path. In a radionuclide production method, the raw material nuclide contained in the liquid is transformed to the radionuclide by irradiating the liquid with the bremsstrahlung radiation while circulating the liquid containing the raw material nuclide in the circulation path, and oxygen and hydrogen generated due to radiolysis of the liquid are removed by a recombination reaction with a metal member formed of the pure metal.
    Type: Application
    Filed: March 17, 2022
    Publication date: May 9, 2024
    Inventors: Takahiro TADOKORO, Yuichiro UENO, Yuuko KANI, Kento NISHIDA, Takahiro WATANABE, Takahiro SASAKI, Masaharu ITO
  • Publication number: 20240126516
    Abstract: A host computer is programmed to receive input specifying definitions of two or more stages, each of the stages representing an attribute of one or more end-user profiles that have undertaken one or more interactions, using computing devices associated with the end-user profiles, with one or more networked computers. For each stage, the user computer can interoperate with a graphical user interface comprising a virtual canvas, a palette comprising a plurality of different graphical icons each representing at least an entry condition and an activation order for digital presentation of information. Visual selection and dragging operations can move copies of an entry condition icon and an activation icon from the palette to the virtual canvas. An entry condition icon is defined using rules to match one or more subsets of the end-user profiles and one or more subsets of the interactions. An activation icon has order attributes order for the digital presentation of information.
    Type: Application
    Filed: June 29, 2023
    Publication date: April 18, 2024
    Inventors: Yili Huang, Alexis Jianghezi Zheng, Nick Kobayashi, Reeba Benzialex, Kai Sasaki, Yuichiro Kaneko
  • Publication number: 20240084893
    Abstract: A power generation system includes: a prime mover; a magnetic gear generator configured to be driven by an input from the prime mover to generate power; a power converter connected to the magnetic gear generator; an operation mode switch unit configured to switch an operation mode of the magnetic gear generator to a step-out avoidance mode in response to that a step-out parameter indicating a risk of step-out of the magnetic gear generator exceeds a prescribed allowable range; and a reduction command unit configured to give the prime mover an input reduction command to reduce the input from the prime mover and configured to give the power converter a torque reduction command to reduce a generator torque of the magnetic gear generator, in the step-out avoidance mode.
    Type: Application
    Filed: February 22, 2022
    Publication date: March 14, 2024
    Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Tsuyoshi Wakasa, Mikito Sasaki, Yuichiro Yazaki, Takatoshi Matsushita, Yoshiki Kato
  • Patent number: 11901356
    Abstract: A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: February 13, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungha Oh, Pil-Kyu Kang, Kughwan Kim, Weonhong Kim, Yuichiro Sasaki, Sang Woo Lee, Sungkeun Lim, Yongho Ha, Sangjin Hyun
  • Publication number: 20230284373
    Abstract: In a circuit board, a printed board includes an insulating base and a plurality of conductors disposed in layers in the insulating base. The conductors include a signal line electrically connected to an electronic component; and a potential fixed layer fixed to a predetermined potential and arranged to face the signal line across the insulating base in a thickness direction of the printed board. The potential fixed layer has a facing surface facing the signal line, and is provided with a high magnetic film having a magnetic permeability higher than that of the at least one potential fixed layer on the facing surface. The high magnetic film is disposed to overlap the signal line in the thickness direction. The signal line includes a facing line that faces the high magnetic film across the insulating base in the thickness direction.
    Type: Application
    Filed: February 10, 2023
    Publication date: September 7, 2023
    Inventors: ERIKO YAZU, RYOSUKE OMURA, KAZUKI TAKAHASHI, KENICHI TAKESHIMA, YUICHIRO SASAKI
  • Patent number: 11728347
    Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: August 15, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Weonhong Kim, Pilkyu Kang, Yuichiro Sasaki, Sungkeun Lim, Yongho Ha, Sangjin Hyun, Kughwan Kim, Seungha Oh
  • Patent number: 11610838
    Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: March 21, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yuichiro Sasaki, Sungkeun Lim, Pil-Kyu Kang, Weonhong Kim, Seungha Oh, Yongho Ha, Sangjin Hyun
  • Publication number: 20220340506
    Abstract: The present invention provides a method for producing 1,3-butadiene that is capable of suppressing generation of reaction by-products. The method includes: a step (A) of to obtain a produced gas containing 1,3-butadiene; a step (B) of cooling the produced gas; and a step (C) of separating the produced gas cooled in the step (B) into molecular oxygen and inert gases, and other gases containing 1,3-butadiene, by selective absorption into an absorption solvent. In the method, in the step (A), the raw material gas and a molecular oxygen-containing gas are supplied to a fixed-bed reactor with a composite oxide catalyst containing molybdenum and bismuth; the molar ratio of molecular oxygen to n-butene in the gases is 1.0 to 2.0; and the molar ratio of water vapor to n-butene in the gases supplied to the fixed-bed reactor is not more than 1.2.
    Type: Application
    Filed: August 26, 2020
    Publication date: October 27, 2022
    Applicants: JSR Corporation, ENEOS Corporation
    Inventors: Junjie WANG, Yuichiro SASAKI, Takashi MORI
  • Publication number: 20220289646
    Abstract: The present invention has as its object the provision of a method for producing 1,3-butadiene capable of efficiently purifying an absorption solvent while a high productivity is assured. A method for producing 1,3-butadiene includes: a step (A) of obtaining a produced gas containing 1,3-butadiene; a step (B) of cooling the produced gas; a step (C) of separating the produced gas, which has been subjected to the step (B); a step (D1) of separating the absorption solvent, that has absorbed an absorption component comprising the other gases containing 1,3 -butadiene into an absorption solvent that does not substantially contain the absorption component and an absorption solvent that contains the absorption component; a step (D2) of separating the absorption solvent that contains the absorption component into an absorption solvent that contains a reaction by-product and a 1,3-butadiene liquid; and a step (E) of purifying the absorption solvent, that contains the reaction by-product.
    Type: Application
    Filed: August 26, 2020
    Publication date: September 15, 2022
    Applicants: JSR Corporation, ENEOS Corporation
    Inventors: Mayu SUGIMOTO, Yuichiro SASAKI
  • Patent number: 11322494
    Abstract: A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 3, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungin Choi, Taehyeon Kim, Hongshik Shin, Taegon Kim, Jaeyoung Park, Yuichiro Sasaki
  • Publication number: 20220028895
    Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.
    Type: Application
    Filed: October 5, 2021
    Publication date: January 27, 2022
    Inventors: Weonhong KIM, Pilkyu KANG, Yuichiro SASAKI, Sungkeun LIM, Yongho HA, Sangjin HYUN, Kughwan KIM, Seungha OH
  • Patent number: 11230513
    Abstract: A process of producing 1,3-butadiene includes: a first step of obtaining gases containing 1,3-butadiene by an oxidative dehydrogenation reaction of a raw material gas with a molecular oxygen-containing gas in the presence of a metal oxide catalyst, the raw material gas containing 1-butene and 2-butene and having a proportion of 2-butene to a sum of 1-butene and 2-butene, which is defined as 100% by volume, being not less than 50% by volume; a second step of cooling the produced gases obtained in the first step; and a third step of separating the produced gases having undergone the second step into molecular oxygen and inert gases and other gases containing 1,3-butadiene by selective absorption to an absorbing solvent, wherein the concentration of methyl vinyl ketone in the produced gases having been cooled in the second step is 0% by volume or more and not more than 0.03% by volume.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: January 25, 2022
    Assignees: JSR Corporation, ENEOS CORPORATION
    Inventors: Mayu Sugimoto, Yuichiro Sasaki, Sosuke Higuchi, Nobuhiro Kimura
  • Patent number: 11177286
    Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: November 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Weonhong Kim, Pilkyu Kang, Yuichiro Sasaki, Sungkeun Lim, Yongho Ha, Sangjin Hyun, Kughwan Kim, Seungha Oh
  • Publication number: 20210335707
    Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.
    Type: Application
    Filed: July 6, 2021
    Publication date: October 28, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yuichiro SASAKI, Sungkeun LIM, Pil-Kyu KANG, Weonhong KIM, Seungha OH, Yongho HA, Sangjin HYUN
  • Patent number: 11121080
    Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 14, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yuichiro Sasaki, Sungkeun Lim, Pil-Kyu Kang, Weonhong Kim, Seungha Oh, Yongho Ha, Sangjin Hyun
  • Publication number: 20210020628
    Abstract: A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).
    Type: Application
    Filed: March 12, 2020
    Publication date: January 21, 2021
    Inventors: SEUNGHA OH, PIL-KYU KANG, KUGHWAN KIM, WEONHONG KIM, YUICHIRO SASAKI, SANG WOO LEE, SUNGKEUN LIM, YONGHO HA, SANGJIN HYUN
  • Publication number: 20210013204
    Abstract: A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.
    Type: Application
    Filed: September 9, 2020
    Publication date: January 14, 2021
    Inventors: KYUNGIN CHOI, Taehyeon KIM, HONGSHIK SHIN, TAEGON KIM, JAEYOUNG PARK, YUICHIRO SASAKI
  • Publication number: 20200399191
    Abstract: A process of producing 1,3-butadiene includes: a first step of obtaining gases containing 1,3-butadiene by an oxidative dehydrogenation reaction of a raw material gas with a molecular oxygen-containing gas in the presence of a metal oxide catalyst, the raw material gas containing 1-butene and 2-butene and having a proportion of 2-butene to a sum of 1-butene and 2-butene, which is defined as 100% by volume, being not less than 50% by volume; a second step of cooling the produced gases obtained in the first step; and a third step of separating the produced gases having undergone the second step into molecular oxygen and inert gases and other gases containing 1,3-butadiene by selective absorption to an absorbing solvent, wherein the concentration of methyl vinyl ketone in the produced gases having been cooled in the second step is 0% by volume or more and not more than 0.03% by volume.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Applicants: JSR Corporation, ENEOS CORPORATION
    Inventors: Mayu SUGIMOTO, Yuichiro SASAKI, Sosuke HIGUCHI, Nobuhiro KIMURA
  • Publication number: 20200373331
    Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.
    Type: Application
    Filed: March 3, 2020
    Publication date: November 26, 2020
    Inventors: Weonhong KIM, Pilkyu KANG, Yuichiro SASAKI, Sungkeun LIM, Yongho HA, Sangjin HYUN, Kughwan KIM, Seungha OH
  • Publication number: 20200365509
    Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.
    Type: Application
    Filed: March 5, 2020
    Publication date: November 19, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yuichiro Sasaki, Sungkeun Lim, Pil-Kyu Kang, Weonhong Kim, Seungha Oh, Yongho Ha, Sangjin Hyun