Patents by Inventor Yuichiro Sasaki

Yuichiro Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804269
    Abstract: A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungin Choi, Taehyeon Kim, Hongshik Shin, Taegon Kim, Jaeyoung Park, Yuichiro Sasaki
  • Patent number: 10490551
    Abstract: A semiconductor device includes: a substrate including a field region that defines an active region; source/drain regions in the active region; a channel region between the source/drain regions; a lightly doped drain (LDD) region between one of the source/drain regions and the channel region; and a gate structure disposed on the channel region. An upper portion of the active region may include an epitaxial growth layer having a larger lattice constant than silicon (Si), and the source/drain regions and the LDD region may be doped with gallium (Ga).
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Shik Shin, Tae-Gon Kim, Yuichiro Sasaki
  • Publication number: 20190287969
    Abstract: A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.
    Type: Application
    Filed: May 22, 2019
    Publication date: September 19, 2019
    Inventors: KYUNGIN CHOI, Taehyeon KIM, HONGSHIK SHIN, TAEGON KIM, JAEYOUNG PARK, YUICHIRO SASAKI
  • Patent number: 10396641
    Abstract: An object is to easily inject resin into a gap of a laminated core which constitutes a rotating electric machine. Included are: a resin supplying unit which feeds the resin; and a resin injection unit which injects the resin into an axial hole of the laminated core. The resin injection unit has an injection pipe and an elastic ring attached to the injection pipe. This elastic ring is made to firmly attach to the inner periphery of the axial hole; the resin is supplied from the resin supplying unit; and the resin is injected into the gap of the laminated core through the axial hole of the laminated core.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: August 27, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Minoru Aoki, Yoshihide Kikuichi, Tetsuro Yanagi, Yuichiro Sasaki, Koji Mio, Hideaki Shigekiyo
  • Patent number: 10355000
    Abstract: A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: July 16, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungin Choi, Taehyeon Kim, Hongshik Shin, Taegon Kim, Jaeyoung Park, Yuichiro Sasaki
  • Publication number: 20190057966
    Abstract: A semiconductor device includes: a substrate including a field region that defines an active region; source/drain regions in the active region; a channel region between the source/drain regions; a lightly doped drain (LDD) region between one of the source/drain regions and the channel region; and a gate structure disposed on the channel region. An upper portion of the active region may include an epitaxial growth layer having a larger lattice constant than silicon (Si), and the source/drain regions and the LDD region may be doped with gallium (Ga).
    Type: Application
    Filed: January 12, 2018
    Publication date: February 21, 2019
    Inventors: HONG-SHIK SHIN, TAE-GON KIM, YUICHIRO SASAKI
  • Patent number: 10164017
    Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: December 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yuichiro Sasaki, Bong Soo Kim, Tae Gon Kim, Yoshiya Moriyama, Seung Hyun Song, Alexander Schmidt, Abraham Yoo, Heung Soon Lee, Kyung In Choi
  • Publication number: 20180286861
    Abstract: A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.
    Type: Application
    Filed: October 25, 2017
    Publication date: October 4, 2018
    Inventors: KYUNGIN CHOI, Taehyeon KIM, HONGSHIK SHIN, TAEGON KIM, JAEYOUNG PARK, YUICHIRO SASAKI
  • Publication number: 20180158911
    Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.
    Type: Application
    Filed: February 2, 2018
    Publication date: June 7, 2018
    Inventors: Yuichiro SASAKI, Bong Soo KIM, Tae Gon KIM, Yoshiya MORIYAMA, Seung Hyun SONG, Alexander SCHMIDT, Abraham YOO, Heung Soon LEE, Kyung In CHOI
  • Patent number: 9911809
    Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: March 6, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yuichiro Sasaki, Bong Soo Kim, Tae Gon Kim, Yoshiya Moriyama, Seung Hyun Song, Alexander Schmidt, Abraham Yoo, Heung Soon Lee, Kyung In Choi
  • Publication number: 20170373151
    Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.
    Type: Application
    Filed: February 3, 2017
    Publication date: December 28, 2017
    Inventors: Yuichiro SASAKI, Bong Soo KIM, Tae Gon KIM, Yoshiya MORIYAMA, Seung Hyun SONG, Alexander SCHMIDT, Abraham YOO, Heung Soon LEE, Kyung In CHOI
  • Publication number: 20150288263
    Abstract: An object is to easily inject resin into a gap of a laminated core which constitutes a rotating electric machine. Included are: a resin supplying unit which feeds the resin; and a resin injection unit which injects the resin into an axial hole of the laminated core. The resin injection unit has an injection pipe and an elastic ring attached to the injection pipe. This elastic ring is made to firmly attach to the inner periphery of the axial hole; the resin is supplied from the resin supplying unit; and the resin is injected into the gap of the laminated core through the axial hole of the laminated core.
    Type: Application
    Filed: January 14, 2014
    Publication date: October 8, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Minoru Aoki, Yoshihide Kikuichi, Tetsuro Yanagi, Yuichiro Sasaki, Koji Mio, Hideaki Shigekiyo
  • Patent number: 8709926
    Abstract: In order to realize a plasma doping method capable of carrying out a stable low-density doping, exhaustion is carried out with a pump while introducing a predetermined gas into a vacuum chamber from a gas supplying apparatus, the pressure of the vacuum chamber is held at a predetermined pressure and a high frequency power is supplied to a coil from a high frequency power source. After the generation of plasma in the vacuum chamber, the pressure of the vacuum chamber is lowered, and the low-density plasma doping is performed to a substrate placed on a substrate electrode. Moreover, the pressure of the vacuum chamber is gradually lowered, and the high frequency power is gradually increased, thereby the low-density plasma doping is carried out to the substrate placed on the substrate electrode.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: April 29, 2014
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Okumura, Ichiro Nakayama, Bunji Mizuno, Yuichiro Sasaki
  • Patent number: 8652953
    Abstract: In a plasma doping device according to the invention, a vacuum chamber is evacuated with a turbo-molecular pump as an exhaust device via a exhaust port while a predetermined gas is being introduced from a gas supply device in order to maintain the inside of the vacuum chamber to a predetermined pressure with a pressure regulating valve. A high-frequency power of 13.56 MHz is supplied by a high-frequency power source to a coil provided in the vicinity of a dielectric window opposed to a sample electrode to generate inductive-coupling plasma in the vacuum chamber. A high-frequency power source for supplying a high-frequency power to the sample electrode is provided. Uniformity of processing is enhanced by driving a gate shutter and covering a through gate.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: February 18, 2014
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Okumura, Yuichiro Sasaki, Katsumi Okashita, Bunji Mizuno, Hiroyuki Ito, Ichiro Nakayama, Cheng-Guo Jin
  • Publication number: 20130323916
    Abstract: A plasma doping apparatus which introduces a predetermined mass flow of gas from a gas supply device into a vacuum chamber while discharging the gas through an exhaust port by a turbo-molecular pump, which is an exhaust device in order to maintain the vacuum chamber under a predetermined pressure by a pressure adjusting valve. A high-frequency power source supplies high-frequency power of 13.56 MHz to a coil disposed in the vicinity of a dielectric window opposite a sample electrode in order to generate an inductively coupled plasma in the vacuum chamber. A sum of an area of an opening of a gas flow-off port opposed to a center portion of the sample electrode is configured to be smaller than that of an area of an opening of the gas flow-off port opposed to a peripheral portion of the sample electrode in order to improve the uniformity.
    Type: Application
    Filed: November 20, 2012
    Publication date: December 5, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Tomohiro OKUMURA, Yuichiro SASAKI, Katsumi OKASHITA, Bunji MIZUNO, Hiroyuki ITO, Ichiro NAKAYAMA, Cheng-Guo JIN
  • Patent number: 8574972
    Abstract: After a fin-semiconductor region (13) is formed on a substrate (11), impurity-containing gas and oxygen-containing gas are used to perform plasma doping on the fin-semiconductor region (13). This forms impurity-doped region (17) in at least side portions of the fin-semiconductor region (13).
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: November 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Masafumi Kubota, Shigenori Hayashi
  • Patent number: 8536000
    Abstract: First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r1? of the upper corner of the first fin-shaped semiconductor region located outside the first gate insulating film is greater than the radius of curvature r1 of the upper corner of the first fin-shaped semiconductor region located under the first gate insulating film and is less than or equal to 2×r1. The radius of curvature r2? of the upper corner of the second fin-shaped semiconductor region located outside the second gate insulating film is greater than the radius of curvature r2 of the upper corner of the second fin-shaped semiconductor region located under the second gate insulating film and is less than or equal to 2×r2.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: September 17, 2013
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Keiichi Nakamoto, Katsumi Okashita, Hisataka Kanada, Bunji Mizuno
  • Patent number: 8409939
    Abstract: A method for fabricating a semiconductor device includes: forming a fin-type semiconductor region on a substrate; and introducing an n-type impurity into at least a side of the fin-type semiconductor region by a plasma doping process, thereby forming an n-type impurity region in the side of the fin-type semiconductor region. In the introducing the n-type impurity, when a source power in the plasma doping process is denoted by a character Y [W], the supply of a gas containing the n-type impurity per unit time and per unit volume is set greater than or equal to 5.1×10?8/((1.72.51/24.51)×(Y/500)) [mol/(min·L·sec)], and the supply of a diluent gas per unit time and per unit volume is set greater than or equal to 1.7×10?4/((202.51/24.51)×(Y/500)) [mol/(min·L·sec)].
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: April 2, 2013
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Katsumi Okashita, Bunji Mizuno
  • Patent number: 8404573
    Abstract: With the evacuation of an interior of a vacuum chamber halted and with gas supply into the vacuum chamber halted, in a state that a mixed gas of helium gas and diborane gas is sealed in the vacuum chamber, a plasma is generated in a vacuum vessel and simultaneously a high-frequency power is supplied to a sample electrode. By the high-frequency power supplied to the sample electrode, boron is introduced to a proximity to a substrate surface.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 26, 2013
    Assignee: Panasonic Corporation
    Inventors: Tomohiro Okumura, Yuichiro Sasaki, Satoshi Maeshima, Ichiro Nakayama, Bunji Mizuno
  • Publication number: 20130022759
    Abstract: With the evacuation of an interior of a vacuum chamber halted and with gas supply into the vacuum chamber halted, in a state that a mixed gas of helium gas and diborane gas is sealed in the vacuum chamber, a plasma is generated in a vacuum vessel and simultaneously a high-frequency power is supplied to a sample electrode. By the high-frequency power supplied to the sample electrode, boron is introduced to a proximity to a substrate surface.
    Type: Application
    Filed: September 12, 2012
    Publication date: January 24, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Tomohiro OKUMURA, Yuichiro SASAKI, Satoshi MAESHIMA, Ichiro NAKAYAMA, Bunji MIZUNO