Patents by Inventor Yuichiro Shimizu

Yuichiro Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090269810
    Abstract: The present invention is a method for enhancing recombinant antibody production by co-expressing in a host cell a recombinant antibody and ERp23 protein, which facilitates oxidative folding and stability of the recombinant antibody thereby enhancing production.
    Type: Application
    Filed: April 15, 2009
    Publication date: October 29, 2009
    Inventors: Yuichiro Shimizu, Linda M. Hendershot
  • Publication number: 20090029506
    Abstract: In a method of manufacturing a semiconductor device 10 including a wiring board 11 having a ground terminal 38, a semiconductor chip 12 and passive components 14 and 15 which are electronic components mounted on the wiring board 11, and a sealing resin 19 containing a silica filler for sealing the semiconductor chip 12 and the passive components 14 and 15, the silica filler present on a surface of the sealing resin 19 is dissolved with a hydrogen fluoride solution, and a shield layer 21 which is electrically connected to the ground terminal 38 is then formed on the surface of the sealing resin 19 by a plating method.
    Type: Application
    Filed: February 6, 2008
    Publication date: January 29, 2009
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Tomoharu Fujii, Yuichiro Shimizu
  • Publication number: 20080236662
    Abstract: In a solar cell module in which a plurality of dye sensitized solar cells is arranged on a plane basis and is connected in series with an intercell region interposed therebetween, a first transparent substrate, a first transparent conductive film, a dye carrying oxide semiconductor layer, an electrolyte layer, a catalyst layer, a second transparent conductive film and a second transparent substrate are laminated, an insulating barrier seals cells on both sides thereof in fluid tightness and insulates them in the intercell region, an electrode connecting portion provided in a central part in a vertical direction of the insulating barrier connects an extended portion of the first transparent conductive film of one of the cells on the both sides to that of a second transparent conductive film of the other cell, and the electrode connecting portion penetrates through at least one of the first transparent substrate and the second transparent substrate in the vertical direction and is thus exposed.
    Type: Application
    Filed: December 10, 2007
    Publication date: October 2, 2008
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Sumihiro Ichikawa, Koji Takei, Noriyoshi Shimizu, Yasunari Suzuki, Ryo Fukasawa, Daisuke Matono, Yuichiro Shimizu
  • Publication number: 20070281366
    Abstract: A mixture of one or more target molecules and functional monomers having functional groups, which are able to interact with the target molecules, is polymerized so as to form a target molecule recognition polymer (MIP) complex to which target molecules are bound, and a functional group which is contained in the MIP complex but is not bound to the target molecule is deactivated. This makes it possible to suppress binding of a non-target molecule that can be bound to the MIP by weak interaction. Thus, it is possible to provide an MIP exhibiting a high selectivity even when high molecular weight molecules like biomolecules are used as the target molecules.
    Type: Application
    Filed: March 15, 2007
    Publication date: December 6, 2007
    Inventors: Yuichiro Shimizu, Takateru Matsunaga
  • Publication number: 20070268048
    Abstract: A power supply control circuit is configured including a MOS-FET 61 connected between a DC power supply 10 and a load circuit 31 so that a body diode D300 formed between the drain and the source is in a forward direction; and a holding circuit 62 for maintaining the ON state of the MOS-FET 61 for a predetermined time when the power supply from the DC power supply 10 is stopped; where heat generation of the switching element by the surge voltage is suppressed when the surge voltage is generated to prevent breakdown of the switching element while preventing breakdown of internal circuits with respect to reverse connection of the power supply.
    Type: Application
    Filed: May 21, 2007
    Publication date: November 22, 2007
    Applicant: Fujitsu Ten Limited
    Inventors: Kazuhiro Komatsu, Yuichiro Shimizu, Daisuke Enomoto
  • Publication number: 20070116594
    Abstract: The detection accuracy and detection reproducibility of an analytical microchip utilizing beads are improved. To this end the analytical microchip has a reaction path 17 having a particle-filled area 19 filled with a group of solid particles, a test-solution introducing path 11 for introducing a test solution into the reaction path, a test-solution discharging path 14 for discharging a test solution inside the reaction path to outside of the microchip, and a particle injection aperture 16 provided on one end side of the reaction path 17. The test-solution discharging path 14 has a direct communication with the particle-filled area 19 in the reaction path 17. The test-solution introducing path 11 has a direct communication with the reaction path 17 on the upper stream side relative to the test-solution discharging path 14 and within the upper-stream-side end surface 22 of the particle-filled area 19.
    Type: Application
    Filed: November 17, 2006
    Publication date: May 24, 2007
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yuichiro Shimizu, Kazuo Hashiguchi
  • Patent number: 7213097
    Abstract: An input processing circuit is interposed between input terminals and input ports of an MPU. An output processing circuit is interposed between output ports of the MPU and output terminals. The input processing circuit includes switch sections and processing sections. The output processing circuit includes switch sections and processing sections. A switch control section switches the switch sections based on switch information stored in a switch information storage section to switch a connection relationship between the input terminals and the input ports, processing for an input signal, a connection relationship between the output ports and the output terminals, and processing for an output signal.
    Type: Grant
    Filed: January 26, 2004
    Date of Patent: May 1, 2007
    Assignee: Fujitsu Ten Limited
    Inventors: Tomohide Kasame, Yoshikazu Hashimoto, Yuichiro Shimizu, Nobunori Asayama, Akio Okahara, Kazuhiro Komatsu, Takashi Higuchi
  • Publication number: 20060256844
    Abstract: A wireless communication device is provided. The wireless communication device executes digital processing for a received UWB signal with use of an A/D converter having an adequate sample rate and resolution, and thus can obtain precise reception timing information. Since the sample rate of an A/D converted output is high, a timing detection circuit is formed of two-stage matched filters. The former-stage chip matched filter calculates the correlation between an input signal and a template signal. When a correct transmission pulse signal has arrived, the chip matched filter outputs to a frame matched filter an indication as to the presence of a pulse and reception timing. The latter-stage frame matched filter calculates the correlation value between a received frame signal and a spreading code to thereby determine whether the received frame is correct or incorrect, and adequately changes a threshold value of the chip matched filter.
    Type: Application
    Filed: May 2, 2006
    Publication date: November 16, 2006
    Applicant: Sony Corporation
    Inventors: Yuichiro Shimizu, Yukitoshi Sanada
  • Publication number: 20040236873
    Abstract: An input processing circuit is interposed between input terminals and input ports of an MPU. An output processing circuit is interposed between output ports of the MPU and output terminals. The input processing circuit includes switch sections and processing sections. The output processing circuit includes switch sections and processing sections. A switch control section switches the switch sections based on switch information stored in a switch information storage section to switch a connection relationship between the input terminals and the input ports, processing for an input signal, a connection relationship between the output ports and the output terminals, and processing for an output signal.
    Type: Application
    Filed: January 26, 2004
    Publication date: November 25, 2004
    Applicant: FUJITSU TEN LIMITED
    Inventors: Tomohide Kasame, Yoshikazu Hashimoto, Yuichiro Shimizu, Nobunori Asayama, Akio Okahara, Kazuhiro Komatsu, Takashi Higuchi