Abstract: A semiconductor memory apparatus including a data memory array, a parity memory array, a data read/write and correction part, a parity read/write part and a syndrome generating and decoding part is provided. The data read/write and correction part reads the data memory array and outputs a first application reading data. The parity read/write part reads the parity memory array and outputs a parity reading data. During a read cycle of an application data, the syndrome generating and decoding part generates a syndrome writing data according to the first application reading data, compares and decodes the syndrome writing data with the parity reading data to generate a verifying comparison data. In the same read cycle, the data read/write and correction part corrects the application data according to the verifying comparison data, and writes the corrected application data back to the data memory array and outputs a corresponding output data.

Abstract: A pseudo static random access memory and a method for writing data thereof are provided. In the method, a basic clock signal having a basic cycle is provided. A chip enable signal is enabled to perform a write operation and write data is received during an enabled time interval of the chip enable signal. A plurality of internal clock signals is generated sequentially at intervals of the basic cycle according to a write command enable signal. A refresh conflict signal is received and it is determined whether the refresh conflict signal is enabled. When the refresh conflict signal is enabled, the internal clock signals are delayed, and the write data is written to a selected sensing amplifier according to the delayed internal clock signals.

Abstract: In a memory apparatus, a data read-write circuit is configured to access data in a memory cell array. A parity-data read-write circuit is configured to access parity data in a parity memory cell array. A syndrome operation circuit generates an error decoding signal according to the data received from the data read-write circuit and the parity data received from the parity data read-write circuit. During the same read period as reading the data, the data read-write circuit corrects an error bit of the data and outputs the corrected data and a correction bit signal according to the error decoding signal. The syndrome operation circuit further outputs a parity data writing signal to the parity data read-write circuit according to the correction bit signal to update the parity data in the parity memory cell array. The data read-write circuit also writes the corrected data back to the memory cell array.

Abstract: A memory device including a self-test circuit, a memory cell array, a power voltage generator, and a redundant row address replacement circuit is provided. The self-test circuit is configured to generate a self-test data signal and a power voltage control signal. The memory cell array receives the self-test data signal and outputs a self-test failure signal. The power voltage generator generates a word line power voltage according to a power voltage control signal. The redundant row address replacement circuit receives the word line power voltage and the self-test failure signal to provide a redundant word line address to the memory cell array. The power voltage generator is configured to provide the word line power voltage in a built-in self-test (BIST) mode to be lower than the word line power voltage in a normal mode.

Abstract: In a memory apparatus, a data read-write circuit is configured to access data in a memory cell array. A parity-data read-write circuit is configured to access parity data in a parity memory cell array. A syndrome operation circuit generates an error decoding signal according to the data received from the data read-write circuit and the parity data received from the parity data read-write circuit. During the same read period as reading the data, the data read-write circuit corrects an error bit of the data and outputs the corrected data and a correction bit signal according to the error decoding signal. The syndrome operation circuit further outputs a parity data writing signal to the parity data read-write circuit according to the correction bit signal to update the parity data in the parity memory cell array. The data read-write circuit also writes the corrected data back to the memory cell array.

Abstract: A memory device includes a data receiver, a latch driver, and a voltage level shifter. The data receiver works in a first voltage, receives an enable signal, a reference signal, and an input data signal, and outputs an internal data signal by the first voltage. The latch driver receives a write select signal and the internal data signal, latches the internal data signal by the first voltage, and outputs at least one latch data signal by a second voltage. The voltage level shifter receives the at least one latch data signal by the second voltage and generates at least one output data signal by the at least one latch data signal. The voltage level shifter sets a voltage value of the at least one output data signal by the first voltage. The voltage value of the first voltage is greater than the voltage value of the second voltage.

Abstract: A semiconductor memory apparatus including a data memory array, a parity memory array, a data read/write and correction part, a parity read/write part and a syndrome generating and decoding part is provided. The data read/write and correction part reads the data memory array and outputs a first application reading data. The parity read/write part reads the parity memory array and outputs a parity reading data. During a read cycle of an application data, the syndrome generating and decoding part generates a syndrome writing data according to the first application reading data, compares and decodes the syndrome writing data with the parity reading data to generate a verifying comparison data. In the same read cycle, the data read/write and correction part corrects the application data according to the verifying comparison data, and writes the corrected application data back to the data memory array and outputs a corresponding output data.

Abstract: A volatile memory device and a self-refresh method thereof are provided. The volatile memory device includes a dynamic memory array. The self-refresh method includes transmit a self-refresh request signal when entering a power saving mode. A voltage boost signal is periodically enabled according to the self-refresh request signal. When the enabled voltage boost signal is detected, an operating voltage for driving a self-refresh operation is pulled up to a self-refresh level. When the operating voltage is pulled up to the self-refresh level, the dynamic memory array is self-refreshed. When the self-refresh operation is completed, the operating voltage is floated.

Abstract: A pseudo static random access memory and a method for writing data thereof are provided. In the method, a basic clock signal having a basic cycle is provided. A chip enable signal is enabled to perform a write operation and write data is received during an enabled time interval of the chip enable signal. A plurality of internal clock signals is generated sequentially at intervals of the basic cycle according to a write command enable signal. A refresh conflict signal is received and it is determined whether the refresh conflict signal is enabled. When the refresh conflict signal is enabled, the internal clock signals are delayed, and the write data is written to a selected sensing amplifier according to the delayed internal clock signals.

Abstract: A memory device and a memory peripheral circuit are provided. The memory peripheral circuit includes a redundancy column data circuit and a column selection control circuit. The redundancy column data circuit is configured to provide a redundancy test mode data signal and a column address signal. The column address signal includes a redundancy column address signal. The column selection control circuit includes a column decoder and a redundancy column decoder. The column decoder disables a bad column address of a main memory block according to the redundancy test mode data signal and the redundancy column address signal. The redundancy column decoder latches the redundancy column address signal, compares the column address signal with the latched redundancy column address to obtain a comparison result, and enables a redundancy column address of a redundancy memory block according to the comparison result.

Abstract: A reverse bias voltage adjuster is provided. The reverse bias voltage adjuster includes an operating voltage generating circuit and a voltage adjusting circuit. The operating voltage generating circuit generates an operating voltage according to a burnin-test signal, a power start signal, and a reverse bias enable signal. In a normal operation mode, the operating voltage is a first voltage value, and in a burnin-test mode, the operating voltage is a second voltage value, wherein the second voltage value is less than the first voltage value. The voltage adjusting circuit is provided with a switch, and in an initial time interval in the burnin-test mode, the voltage adjusting circuit adjusts voltage value of the reverse bias by turning on the switch.

Abstract: A reverse bias voltage adjuster is provided. The reverse bias voltage adjuster includes an operating voltage generating circuit and a voltage adjusting circuit. The operating voltage generating circuit generates an operating voltage according to a burnin-test signal, a power start signal, and a reverse bias enable signal. In a normal operation mode, the operating voltage is a first voltage value, and in a burnin-test mode, the operating voltage is a second voltage value, wherein the second voltage value is less than the first voltage value. The voltage adjusting circuit is provided with a switch, and in an initial time interval in the burnin-test mode, the voltage adjusting circuit adjusts voltage value of the reverse bias by turning on the switch.

Abstract: A memory apparatus and a majority detector thereof are provided. The majority detector includes a pull-up circuit, a first switch, a second switch, a plurality of first transistors, a plurality of second transistors and a sense amplifying circuit. The pull-up circuit provides a first voltage to a first node and a second node according to a control signal before a sensing period. The first switch and the second switch provide a second voltage to the first node and the second node respectively according to the control signal during the sensing period. Control ends of the first transistors each receives one of a plurality of values of a data signal. Control ends of the second transistors each receives an inverse value of the one of the values of the data signal. The sense amplifying circuit generates a sensing result according to a voltage difference between the first node and the second node during the sensing period, and the sensing result indicates a majority value among the values.

Abstract: A memory device is provided, including a built-in self-test circuit and a redundancy address replacement circuit. The built-in self-test circuit coupled to a main memory cell array is configured to performing a built-in self-test process on the main memory cell array so as to provide a built-in self-test signal. The redundancy address replacement circuit includes a first redundancy circuit and a second redundancy circuit. The first redundancy circuit replaces portion of word line addresses of the main memory cell array with that of a redundancy memory block according to first redundancy data signals generated by a first test process. The second redundancy circuit, coupled to the first redundancy circuit, replaces the failure word line addresses detected in the main memory cell array with another portion of word line addresses of the redundancy memory block according to the built-in self-test signal.

Abstract: A memory device including a self-test circuit, a memory cell array, a power voltage generator, and a redundant row address replacement circuit is provided. The self-test circuit is configured to generate a self-test data signal and a power voltage control signal. The memory cell array receives the self-test data signal and outputs a self-test failure signal. The power voltage generator generates a word line power voltage according to a power voltage control signal. The redundant row address replacement circuit receives the word line power voltage and the self-test failure signal to provide a redundant word line address to the memory cell array. The power voltage generator is configured to provide the word line power voltage in a built-in self-test (BIST) mode to be lower than the word line power voltage in a normal mode.

Abstract: A memory device includes a data receiver, a latch driver, and a voltage level shifter. The data receiver works in a first voltage, receives an enable signal, a reference signal, and an input data signal, and outputs an internal data signal by the first voltage. The latch driver receives a write select signal and the internal data signal, latches the internal data signal by the first voltage, and outputs at least one latch data signal by a second voltage. The voltage level shifter receives the at least one latch data signal by the second voltage and generates at least one output data signal by the at least one latch data signal. The voltage level shifter sets a voltage value of the at least one output data signal by the first voltage. The voltage value of the first voltage is greater than the voltage value of the second voltage.

Abstract: A memory device and a data refreshing method of the memory device are provided. The memory device includes a memory array and a memory control circuit. The memory control circuit counts the number of access commands to generate a first count value and counts the number of refreshing commands to generate a second count value. If the first count value is equal to the second count value, the memory control circuit latches a memory bank address and a memory row address corresponding to the access commands to obtain a row hammer refreshing bank address and a row hammer refreshing row address. The memory control circuit performs a row hammer refreshing operation on a memory bank according to the row hammer refreshing bank address and the row hammer refreshing row address.

Abstract: A memory device is provided. The memory device includes at least one memory bank, at least one first address decoder set, and at least one second address decoder set. Each of the at least one memory bank includes a plurality of memory cell arrays. Each of the at least one second address decoder set includes a plurality of second address decoders. The at least one second address decoder set receives a plurality of column select lines to perform an access operation on memory cells of the memory cell arrays. The column select lines are divided into a plurality of column select line groups, and each of the column select line groups is assigned to the second address decoder corresponding thereto, wherein the number of the column select lines allocated to each of the column select line groups is less than a total number of the column select lines.

Abstract: A memory device and a method for test reading and writing thereof are provided. A precharge voltage control circuit is based on the precharge reference voltage to provide a first precharge voltage and a second precharge voltage. A sense amplifier circuit is coupled between a bit line and a complementary bit line and configured to sense data of a memory cell coupled to the bit line, and also coupled to the precharge voltage control circuit to make the bit line and the complementary bit line receive the first precharge voltage and the second precharge voltage respectively, the first precharge voltage and the second precharge voltage are on the same voltage level during the precharge operation, but during a test write sensing period and a test read sensing period after the precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage are different.

Abstract: A memory device and a method for test reading and writing thereof are provided. A precharge voltage control circuit is based on the precharge reference voltage to provide a first precharge voltage and a second precharge voltage. A sense amplifier circuit is coupled between a bit line and a complementary bit line and configured to sense data of a memory cell coupled to the bit line, and also coupled to the precharge voltage control circuit to make the bit line and the complementary bit line receive the first precharge voltage and the second precharge voltage respectively, the first precharge voltage and the second precharge voltage are on the same voltage level during the precharge operation, but during a test write sensing period and a test read sensing period after the precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage are different.