Abstract: When an I/O number is 8 bit, a semiconductor device includes a first memory mat that is selected when X13 is (0) and X11 and X12 are (0, 0), a second memory mat that is selected when X13 is (1) and X11 and X12 are (0, 0), and a third memory mat that is selected irrespective of a value of X13 when X11 and X12 are (0, 0). When the I/O number is 16 bit, X13 is ignored, and the first to third memory mats are selected when X11 and X12 are (0, 0). In this manner, because the third memory mat is shared between so-called upper side and lower side, control is prevented from becoming complicated and an area is prevented from increasing.

Abstract: The semiconductor memory device proposed in the present invention comprises the buffer control circuit which, when writing the data, controls the data input buffer so that the data from the same timing as the clock when the writing command is input is written in the activated memory bank, and which, when reading the data, controls the data output buffer so that the data with the read latency of more than 3 clock cycles after when the reading command is input is read from the activated memory bank.

Abstract: The semiconductor memory device proposed in the present invention comprises memory cells disposed in the row direction and the column direction, a plurality of first lines by which supply voltages are supplied in order to select memory cells disposed in the row direction among the plurality of cells, a plurality of second lines by which supply voltages are supplied in order to select memory cells disposed in the column direction among the plurality of cells, the data lines which input and output the data to the selected memory cells, the first power voltage supply circuit which supplies the predetermined supply voltages to the first lines corresponding with the externally input row address synchronizing with an act command, and the second power voltage supply circuit which supplies the predetermined supply voltages to the second lines corresponding with the externally input column address synchronizing with an act command.

Abstract: In order to generate internal addresses from an external address in a burst operation in a synchronous dynamic random access memory (SDRAM), an external address is latched in response to an external clock signal. First and second control signals are generated in synchronous with the external clock signal. An internal address for a first clock cycle of a burst operation is generated from the latched external address in a sequential mode in response to the first control signal using a first transfer path. An internal address for each of a second clock cycle and subsequent clock cycles of the burst operation in the sequential mode is generated in response to a second control signal using a second transfer path such that the internal address for each of the second clock cycle and subsequent clock cycles has substantially the same delay time as that of the internal address for the first clock cycle with respect to the external clock signal.

Abstract: A semiconductor memory device of the present invention comprises, a first memory cell 110, a first data line DLN connected to the first memory cell, a second data line IOT, a first select signal CSL(E) controlling connection/disconnection between the first data line and the second data line, a second memory cell 112, a third data line DTN connected to the second memory cell, a fourth data line IOT, a second select signal CSL (O) controlling connection/disconnection between the third data line and the fourth data line, wherein a timing selecting the first and second memory cells at the writing operation is the same of a timing selecting the first and second memory cells at the reading operation.

Abstract: A semiconductor memory device is tested in a bit-compressed test mode wherein a plurality of banks of memory cells, which are disposed in association with respective I/O pins, are tested through one of the I/O pins. During the bit-compressed test mode, a check mode is additionally entered to examine whether the memory device actually stays in the bit-compressed test mode. The result of check by the check mode is supplied through the one of the I/Os pin delegating the plurality of I/O pins. The bit-compressed test mode is effected with accuracy.

Abstract: In a memory in which a memory cell array 200 and a subword drive circuit SWD are alternately arranged in a row direction in addition to an SA array 170 and a cross portion (SWC) alternately arranged, there are arranged an interface circuit 100 between a global I/O line GIOT/B and a local I/O line LIOT/B in a first cross portion SWD1, nMOSs Q2, Q4, and Q5of an SA control circuit in a second cross portion SWC2, and pMOSs Q1 and Q3 of the SA control circuit in a third cross portion SWC3.

Abstract: The semiconductor memory device comprises a memory array (9) and a data bus line (1) for transferring read and write data between the memory array and an input buffer (IB) and an output buffer (OB) and also transferring an information indicating read or write mode operation. The data bus line transfers the read data as a complement signal having a predetermined amplitude which is smaller than a potential difference between high and low level power source lines (7 and 8, respectively). The predetermined amplitude is defined by a first and a second impedance (2 and 3, respectively) connected between the data bus line and a first and a second power source line (7 and 8), respectively, The first impedance (2) is associated with a first end of the data bus line in the input-output buffer area and the second impedance (3) is associated with a second end of the data bus line in the inner circuit area of the device.

Abstract: A semiconductor memory device including data bus lines each having one single wire line, and balance circuits each having an inverter for inverting a corresponding level of the data bus line, a capacitor which is connected at one end with the inverter and at the other end with a power source and has a capacitance substantially similar to the parasitic capacitance of the data bus line, and a transfer gate which receives control signals at a control terminal thereof connected between an end of the capacitor and the data bus line. The balance circuits set the potential level of the respective data bus line at an intermediate level between the power source potential and the ground potential. By structuring the device as above, data could be read out or written in by the data bus line provided in a one-to-one relation with one bit of input/output data to thereby reduce the area of the regions where data bus lines should be placed without impairing the operational speed.

Abstract: For preventing a power consuming circuit from undesirable operation upon a power on event, there is disclosed a prohibition circuit operative to produce a control signal supplied to the power consuming circuit for a prohibition of an operation carried out by the power consuming circuit on the basis of an external signal, the prohibition circuit comprises a raw control signal producing circuit operative to produce a raw control signal shifted from an inactive voltage level to an active voltage level after the power switch on event, the raw control signal is shifted from the active voltage level to the inactive voltage level when a power voltage level excesses a certain voltage level, the prohibition circuit further comprises an adjusting circuit responsive to the raw control signal and the external control signal and operative to produce the control signal of the active voltage level when the raw control signal is shifted from the inactive voltage level to the active voltage level regardless of the voltage lev

Abstract: The semiconductor memory device comprises a memory array (9) and a data bus line (1) for transferring read and write data between the memory array and an input buffer (IB) and an output buffer (OB) and also transferring an information indicating read or write mode operation. The data bus line transfers the read data as a complement signal having a predetermined amplitude which is smaller than a potential difference between high and low level power source lines (7 and 8, respectively). The predetermined amplitude is defined by a first and a second impedance (2 and 3, respectively) connected between the data bus line and a first and a second power source line (7 and 8), respectively, The first impedance (2) is associated with a first end of the data bus line in the input-output buffer area and the second impedance (3) is associated with a second end of the data bus line in the inner circuit area of the device.