Abstract: A memory device and a memory peripheral circuit are provided. The memory peripheral circuit includes a redundancy column data circuit and a column selection control circuit. The redundancy column data circuit is configured to provide a redundancy test mode data signal and a column address signal. The column address signal includes a redundancy column address signal. The column selection control circuit includes a column decoder and a redundancy column decoder. The column decoder disables a bad column address of a main memory block according to the redundancy test mode data signal and the redundancy column address signal. The redundancy column decoder latches the redundancy column address signal, compares the column address signal with the latched redundancy column address to obtain a comparison result, and enables a redundancy column address of a redundancy memory block according to the comparison result.

Abstract: A memory device is provided, including a built-in self-test circuit and a redundancy address replacement circuit. The built-in self-test circuit coupled to a main memory cell array is configured to performing a built-in self-test process on the main memory cell array so as to provide a built-in self-test signal. The redundancy address replacement circuit includes a first redundancy circuit and a second redundancy circuit. The first redundancy circuit replaces portion of word line addresses of the main memory cell array with that of a redundancy memory block according to first redundancy data signals generated by a first test process. The second redundancy circuit, coupled to the first redundancy circuit, replaces the failure word line addresses detected in the main memory cell array with another portion of word line addresses of the redundancy memory block according to the built-in self-test signal.

Abstract: A memory apparatus and a majority detector thereof are provided. The majority detector includes a pull-up circuit, a first switch, a second switch, a plurality of first transistors, a plurality of second transistors and a sense amplifying circuit. The pull-up circuit provides a first voltage to a first node and a second node according to a control signal before a sensing period. The first switch and the second switch provide a second voltage to the first node and the second node respectively according to the control signal during the sensing period. Control ends of the first transistors each receives one of a plurality of values of a data signal. Control ends of the second transistors each receives an inverse value of the one of the values of the data signal. The sense amplifying circuit generates a sensing result according to a voltage difference between the first node and the second node during the sensing period, and the sensing result indicates a majority value among the values.

Abstract: A memory device and a data refreshing method of the memory device are provided. The memory device includes a memory array and a memory control circuit. The memory control circuit counts the number of access commands to generate a first count value and counts the number of refreshing commands to generate a second count value. If the first count value is equal to the second count value, the memory control circuit latches a memory bank address and a memory row address corresponding to the access commands to obtain a row hammer refreshing bank address and a row hammer refreshing row address. The memory control circuit performs a row hammer refreshing operation on a memory bank according to the row hammer refreshing bank address and the row hammer refreshing row address.

Abstract: A memory device and a data refreshing method thereof are provided. When an automatic refresh word line address and a row hammer refresh word line address belong to the same memory cell array, memory cells corresponding to the automatic refresh word line address are refreshed, and a time to refresh memory cells corresponding to the row hammer refresh word line address is postponed.

Abstract: A pseudo static random access memory (SRAM) and a refresh method for a pseudo SRAM are provided. The refresh method includes: providing a basic clock signal; at a first time point, enabling a chip enable signal to perform a first write operation, and receiving write data during an enabled time period of the chip enable signal; at a delay time point after the first time point, enabling a sub-word line driving signal, and writing the write data to at least one selected sense amplifier during an enabled time period of the sub-word line driving signal; and receiving a refresh request signal, and determining whether the refresh request signal is enabled according to an end time point of the enabled time period of the chip enable signal to determine a timing of starting a refresh operation.

Abstract: A memory device and a data refreshing method thereof are provided. When an automatic refresh word line address and a row hammer refresh word line address belong to the same memory cell array, memory cells corresponding to the automatic refresh word line address are refreshed, and a time to refresh memory cells corresponding to the row hammer refresh word line address is postponed.

Abstract: A memory device is provided. The memory device includes at least one memory bank, at least one first address decoder set, and at least one second address decoder set. Each of the at least one memory bank includes a plurality of memory cell arrays. Each of the at least one second address decoder set includes a plurality of second address decoders. The at least one second address decoder set receives a plurality of column select lines to perform an access operation on memory cells of the memory cell arrays. The column select lines are divided into a plurality of column select line groups, and each of the column select line groups is assigned to the second address decoder corresponding thereto, wherein the number of the column select lines allocated to each of the column select line groups is less than a total number of the column select lines.

Abstract: A volatile memory device and a self-refresh method thereof are provided. The volatile memory device includes a dynamic memory array. The self-refresh method includes transmit a self-refresh request signal when entering a power saving mode. A voltage boost signal is periodically enabled according to the self-refresh request signal. When the enabled voltage boost signal is detected, an operating voltage for driving a self-refresh operation is pulled up to a self-refresh level. When the operating voltage is pulled up to the self-refresh level, the dynamic memory array is self-refreshed. When the self-refresh operation is completed, the operating voltage is floated.

Abstract: A pseudo static random access memory (SRAM) and a refresh method for a pseudo SRAM are provided. The refresh method includes: providing a basic clock signal; at a first time point, enabling a chip enable signal to perform a first write operation, and receiving write data during an enabled time period of the chip enable signal; at a delay time point after the first time point, enabling a sub-word line driving signal, and writing the write data to at least one selected sense amplifier during an enabled time period of the sub-word line driving signal; and receiving a refresh request signal, and determining whether the refresh request signal is enabled according to an end time point of the enabled time period of the chip enable signal to determine a timing of starting a refresh operation.

Abstract: A memory device is provided. The memory device includes a first chip and a second chip. The first chip includes a first memory array, a first signal buffer and a plurality of first pads. The second chip includes a second memory array, a second signal buffer and a plurality of second pads. The second signal buffer is coupled to the first signal buffer by at least one connection wire, and the at least one connection wire passes through a scribe line between the first chip and the second chip. When the scribe line between the first chip and the second chip is not cut, signals are transmitted between the first signal buffer and the second signal buffer via the at least one connection wire, and the first memory array and the second memory array are commonly connected to the first pads and not connected to the second pads.

Abstract: A semiconductor device comprises a first pair of signal lines and a first control circuit. The first control circuit precharges each of the first pair of signal lines to a first voltage in response to a precharge signal, and changes the voltage level of each of the first pair of signal lines to a second voltage different from the first voltage when a deep power down signal is input.

Abstract: A semiconductor device comprises a first pair of signal lines and a first control circuit. The first control circuit precharges each of the first pair of signal lines to a first voltage in response to a precharge signal, and changes the voltage level of each of the first pair of signal lines to a second voltage different from the first voltage when a deep power down signal is input.

Abstract: A semiconductor device comprises a first pair of signal lines and a first control circuit. The first control circuit precharges each of the first pair of signal lines to a first voltage in response to a precharge signal, and changes the voltage level of each of the first pair of signal lines to a second voltage different from the first voltage when a deep power down signal is input.

Abstract: When overdriving a first power supply voltage supplied to a sense amplifier, a line for the first power supply voltage and a line for a second power supply voltage which is higher than the first power supply voltage are connected to each other by a first transistor, thereby boosting the first power supply voltage. When the first power supply voltage drops upon activation of the sense amplifier, the line for the first power supply voltage and the line for the second power supply voltage are connected to each other by a second transistor, thereby increasing the current supply capability. The first transistor and the second transistor are fully driven to operate as switches.

Abstract: When an I/O number is 8 bit, a semiconductor device includes a first memory mat that is selected when X13 is (0) and X11 and X12 are (0, 0), a second memory mat that is selected when X13 is (1) and X11 and X12 are (0, 0), and a third memory mat that is selected irrespective of a value of X13 when X11 and X12 are (0, 0). When the I/O number is 16 bit, X13 is ignored, and the first to third memory mats are selected when X11 and X12 are (0, 0). In this manner, because the third memory mat is shared between so-called upper side and lower side, control is prevented from becoming complicated and an area is prevented from increasing.

Abstract: Disclosed is a semiconductor device including: a first switch controlling connection between a first data line pair a second data line pair; a first amplifier connected to the first data line pair; a second switch controlling the connection between the second data line pair and a third data line pair; a second amplifier amplifying data on the second data line pair and delivering the amplified data to the third data line pair; a third amplifier connected to the third data line pair; and a switch control circuit controlling the second switch. Based upon a first control signal that controls precharging and equalization of the first data line pair, the switch control circuit renders the second switch conductive when precharging and equalization of the first data line pair is not carried out, and renders the second switch non-conductive when precharging and equalization of the first data line pair is carried out.

Abstract: Disclosed is a semiconductor device including: a first switch controlling connection between a first data line pair a second data line pair; a first amplifier connected to the first data line pair; a second switch controlling the connection between the second data line pair and a third data line pair; a second amplifier amplifying data on the second data line pair and delivering the amplified data to the third data line pair; a third amplifier connected to the third data line pair; and a switch control circuit controlling the second switch. Based upon a first control signal that controls precharging and equalization of the first data line pair, the switch control circuit renders the second switch conductive when precharging and equalization of the first data line pair is not carried out, and renders the second switch non-conductive when precharging and equalization of the first data line pair is carried out.

Abstract: A renewal of an internal address generated by an internal address generator that is used for a refresh operation of information in a memory unit including a plurality of memory cells is preformed during a refresh operation before an activated word line connected to the memory cell corresponding to the internal address is inactivated in the refresh operation.

Abstract: When overdriving a first power supply voltage supplied to a sense amplifier, a line for the first power supply voltage and a line for a second power supply voltage which is higher than the first power supply voltage are connected to each other by a first transistor, thereby boosting the first power supply voltage. When the first power supply voltage drops upon activation of the sense amplifier, the line for the first power supply voltage and the line for the second power supply voltage are connected to each other by a second transistor, thereby increasing the current supply capability. The first transistor and the second transistor are fully driven to operate as switches.