Patents by Inventor Yuji Yatsuda
Yuji Yatsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120241856Abstract: In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.Type: ApplicationFiled: June 1, 2012Publication date: September 27, 2012Inventors: Yoshito NAKAZAWA, Yuji YATSUDA
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Patent number: 8232610Abstract: In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.Type: GrantFiled: September 1, 2010Date of Patent: July 31, 2012Assignee: Renesas Electronics CorporationInventors: Yoshito Nakazawa, Yuji Yatsuda
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Publication number: 20110233665Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.Type: ApplicationFiled: June 3, 2011Publication date: September 29, 2011Inventors: HITOSHI MATSUURA, Yoshito Nakazawa, Tsuyoshi Kachi, Yuji Yatsuda
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Patent number: 7968939Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.Type: GrantFiled: November 28, 2010Date of Patent: June 28, 2011Assignee: Renesas Electronics CorporationInventors: Hitoshi Matsuura, Yoshito Nakazawa, Tsuyoshi Kachi, Yuji Yatsuda
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Publication number: 20110068392Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.Type: ApplicationFiled: November 28, 2010Publication date: March 24, 2011Inventors: HITOSHI MATSUURA, Yoshito Nakazawa, Tsuyoshi Kachi, Yuji Yatsuda
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Publication number: 20100327359Abstract: In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.Type: ApplicationFiled: September 1, 2010Publication date: December 30, 2010Inventors: Yoshito NAKAZAWA, Yuji Yatsuda
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Patent number: 7847347Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.Type: GrantFiled: March 15, 2010Date of Patent: December 7, 2010Assignee: Renesas Electronics CorporationInventors: Hitoshi Matsuura, Yoshito Nakazawa, Tsuyoshi Kachi, Yuji Yatsuda
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Patent number: 7834407Abstract: In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.Type: GrantFiled: May 26, 2009Date of Patent: November 16, 2010Assignee: Renesas Electronics CorporationInventors: Yoshito Nakazawa, Yuji Yatsuda
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Patent number: 7759730Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.Type: GrantFiled: May 11, 2009Date of Patent: July 20, 2010Assignee: Renesas Technology Corp.Inventors: Hitoshi Matsuura, Yoshito Nakazawa, Tsuyoshi Kachi, Yuji Yatsuda
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Publication number: 20100171174Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.Type: ApplicationFiled: March 15, 2010Publication date: July 8, 2010Inventors: HITOSHI MATSUURA, Yoshito Nakazawa, Tsuyoshi Kachi, Yuji Yatsuda
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Publication number: 20090230467Abstract: In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.Type: ApplicationFiled: May 26, 2009Publication date: September 17, 2009Inventors: Yoshito Nakazawa, Yuji Yatsuda
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Publication number: 20090224315Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.Type: ApplicationFiled: May 11, 2009Publication date: September 10, 2009Inventors: Hitoshi Matsuura, Yoshito Nakazawa, Tsuyoshi Kachi, Yuji Yatsuda
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Patent number: 7544568Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.Type: GrantFiled: August 9, 2007Date of Patent: June 9, 2009Assignee: Renesas Technology Corp.Inventors: Hitoshi Matsuura, Yoshito Nakazawa, Tsuyoshi Kachi, Yuji Yatsuda
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Patent number: 7518183Abstract: Heightening of breakdown voltage of a trench gate type power MISFET is actualized without increasing the number of manufacturing steps. In the manufacturing method of the semiconductor device according to the present invention, p? type semiconductor region and p? type field limiting rings are formed in a gate line area simultaneously in one impurity ion implantation step so as to bring them into contact with a groove having a gate extraction electrode formed therein. Upon formation, supposing that the width of the gate extraction electrode disposed outside the groove is CHSP, and the resistivity of the n? type single crystal silicon layer 1B is ? (?·cm) the CHSP is sets to satisfy the following equation: CHSP?3.80+0.148?.Type: GrantFiled: April 5, 2006Date of Patent: April 14, 2009Assignee: Renesas Technology Corp.Inventors: Yoshito Nakazawa, Yuji Yatsuda
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Publication number: 20080035990Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.Type: ApplicationFiled: August 9, 2007Publication date: February 14, 2008Inventors: Hitoshi Matsuura, Yoshito Nakazawa, Tsuyoshi Kachi, Yuji Yatsuda
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Patent number: 7211862Abstract: A semiconductor device wherein an avalanche withstand of power MISFET is improved without enlarging cell pitch. In the semiconductor device, impurity ions having a p-type conduction, e.g. B ions, are introduced from a bottom of a contact hole to form a p-type semiconductive region that is provided below a p+-type semiconductive region and in contact with the p+-type semiconductive region and an n?-type single crystal silicon layer and that has an impurity concentration lower than the p+-type semiconductive region. An n-type semiconductive region is formed in the n?-type single crystal silicon layer provided below the p-type semiconductive region as being in contact with the p-type semiconductive region and has an impurity concentration lower than the n?-type single crystal silicon layer.Type: GrantFiled: October 14, 2005Date of Patent: May 1, 2007Assignee: Renesas Technology Corp.Inventors: Yoshito Nakazawa, Yuji Yatsuda
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Publication number: 20060261391Abstract: In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.Type: ApplicationFiled: May 12, 2006Publication date: November 23, 2006Inventors: Yoshito Nakazawa, Yuji Yatsuda
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Publication number: 20060180856Abstract: Heightening of breakdown voltage of a trench gate type power MISFET is actualized without increasing the number of manufacturing steps. In the manufacturing method of the semiconductor device according to the present invention, p? type semiconductor region and p? type field limiting rings are formed in a gate line area simultaneously in one impurity ion implantation step so as to bring them into contact with a groove having a gate extraction electrode formed therein. Upon formation, supposing that the width of the gate extraction electrode disposed outside the groove is CHSP, and the resistivity of the n? type single crystal silicon layer 1B is ? (?·cm) the CHSP is sets to satisfy the following equation: CHSP?3.80+0.148?.Type: ApplicationFiled: April 5, 2006Publication date: August 17, 2006Inventors: Yoshito Nakazawa, Yuji Yatsuda
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Patent number: 7042048Abstract: Heightening of breakdown voltage of a trench gate type power MISFET is actualized without increasing the number of manufacturing steps. In the manufacturing method of the semiconductor device according to the present invention, p? type semiconductor region and p? type field limiting rings are formed in a gate line area simultaneously in one impurity ion implantation step so as to bring them into contact with a groove having a gate extraction electrode formed therein. Upon formation, supposing that the width of the gate extraction electrode disposed outside the groove is CHSP, and the resistivity of the n? type single crystal silicon layer 1B is ? (?·cm), the CHSP is set to satisfy the following equation: CHSP?3.80+0.148?.Type: GrantFiled: April 4, 2005Date of Patent: May 9, 2006Assignee: Renesas Technology CorporationInventors: Yoshito Nakazawa, Yuji Yatsuda
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Publication number: 20060027862Abstract: A semiconductor device wherein an avalanche withstand of power MISFET is improved without enlarging cell pitch. In the semiconductor device, impurity ions having a p-type conduction, e.g. B ions, are introduced from a bottom of a contact hole to form a p-type semiconductive region that is provided below a p+-type semiconductive region and in contact with the p+-type semiconductive region and an n?-type single crystal silicon layer and that has an impurity concentration lower than the p+-type semiconductive region. An n-type semiconductive region is formed in the n?-type single crystal silicon layer provided below the p-type semiconductive region as being in contact with the p-type semiconductive region and has an impurity concentration lower than the n?-type single crystal silicon layer.Type: ApplicationFiled: October 14, 2005Publication date: February 9, 2006Inventors: Yoshito Nakazawa, Yuji Yatsuda