Patents by Inventor Yuji Yatsuda
Yuji Yatsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6977416Abstract: A semiconductor device wherein an avalanche withstand of power MISFET is improved without enlarging cell pitch. In the semiconductor device, impurity ions having a p-type conduction, e.g. B ions, are introduced from a bottom of a contact hole to form a p-type semiconductive region that is provided below a p+-type semiconductive region and in contact with the p+-type semiconductive region and an n?-type single crystal silicon layer and that has an impurity concentration lower than the p+-type semiconductive region. An n-type semiconductive region is formed in the n?-type single crystal silicon layer provided below the p-type semiconductive region as being in contact with the p-type semiconductive region and has an impurity concentration lower than the n?-type single crystal silicon layer.Type: GrantFiled: July 7, 2004Date of Patent: December 20, 2005Assignee: Renesas Technology Corp.Inventors: Yoshito Nakazawa, Yuji Yatsuda
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Publication number: 20050167746Abstract: Heightening of breakdown voltage of a trench gate type power MISFET is actualized without increasing the number of manufacturing steps. In the manufacturing method of the semiconductor device according to the present invention, p? type semiconductor region and p? type field limiting rings are formed in a gate line area simultaneously in one impurity ion implantation step so as to bring them into contact with a groove having a gate extraction electrode formed therein. Upon formation, supposing that the width of the gate extraction electrode disposed outside the groove is CHSP, and the resistivity of the n? type single crystal silicon layer 1B is ? (?·cm), the CHSP is set to satisfy the following equation: CHSP?3.80+0.14892 .Type: ApplicationFiled: April 4, 2005Publication date: August 4, 2005Inventors: Yoshito Nakazawa, Yuji Yatsuda
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Patent number: 6885061Abstract: Heightening of breakdown voltage of a trench gate type power MISFET is actualized without increasing the number of manufacturing steps. In the manufacturing method of the semiconductor device according to the present invention, p? type semiconductor region and p? type field limiting rings are formed in a gate line area simultaneously in one impurity ion implantation step so as to bring them into contact with a groove having a gate extraction electrode formed therein. Upon formation, supposing that the width of the gate extraction electrode disposed outside the groove is CHSP, and the resistivity of the n? type single crystal silicon layer 1B is ? (?·cm), the CHSP is set to satisfy the following equation: CHSP?3.80+0.148 ?.Type: GrantFiled: April 20, 2004Date of Patent: April 26, 2005Assignee: Renesas Technology Corp.Inventors: Yoshito Nakazawa, Yuji Yatsuda
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Publication number: 20050032287Abstract: A semiconductor device wherein an avalanche withstand of power MISFET is improved without enlarging cell pitch. In the semiconductor device, impurity ions having a p-type conduction, e.g. B ions, are introduced from a bottom of a contact hole to form a p-type semiconductive region that is provided below a p+-type semiconductive region and in contact with the p+-type semiconductive region and an n?-type single crystal silicon layer and that has an impurity concentration lower than the p+-type semiconductive region. An n-type semiconductive region is formed in the n?-type single crystal silicon layer provided below the p-type semiconductive region as being in contact with the p-type semiconductive region and has an impurity concentration lower than the n?-type single crystal silicon layer.Type: ApplicationFiled: July 7, 2004Publication date: February 10, 2005Inventors: Yoshito Nakazawa, Yuji Yatsuda
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Publication number: 20040262678Abstract: Heightening of breakdown voltage of a trench gate type power MISFET is actualized without increasing the number of manufacturing steps. In the manufacturing method of the semiconductor device according to the present invention, p− type semiconductor region and p− type field limiting rings are formed in a gate line area simultaneously in one impurity ion implantation step so as to bring them into contact with a groove having a gate extraction electrode formed therein. Upon formation, supposing that the width of the gate extraction electrode disposed outside the groove is CHSP, and the resistivity of the n− type single crystal silicon layer 1B is &rgr; (&OHgr;•cm), the CHSP is set to satisfy the following equation: CHSP≦3.80+0.148&rgr;.Type: ApplicationFiled: April 20, 2004Publication date: December 30, 2004Applicant: Renesas Technology Corp.Inventors: Yoshito Nakazawa, Yuji Yatsuda
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Patent number: 6492689Abstract: In a driving power IC including a starter circuit comprising a main-switch (MS) transistor, a starter switch (SS) for starting the MS transistor and a start resistor (or a resistor element) SR, the start resistor is created on a field insulation film. In a periphery area of a chip for integrating the driving power IC, that is, on a semiconductor substrate's surface beneath the field insulation film, field limiting rings (FLRS) are created, enclosing an active area in a multiplexed state. The resistor element is extended from a start edge on the inner side of a group of said field limiting rings to an end edge on the outer side of the group, having a zigzag shape.Type: GrantFiled: April 26, 2001Date of Patent: December 10, 2002Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.Inventors: Shunichi Yamauchi, Yoshito Nakazawa, Yuji Yatsuda
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Publication number: 20010035554Abstract: In a driving power IC including a starter circuit comprising a main-switch (MS) transistor, a starter switch (SS) for starting the MS transistor and a start resistor (or a resistor element) SR, the start resistor is created on a field insulation film. In a periphery area of a chip for integrating the driving power IC, that is, on a semiconductor substrate's surface beneath the field insulation film, field limiting rings (FLRs) are created, enclosing an active area in a multiplexed state. The resistor element is extended from a start edge on the inner side of a group of said field limiting rings to an end edge on the outer side of the group, having a zigzag shape.Type: ApplicationFiled: April 26, 2001Publication date: November 1, 2001Inventors: Shunichi Yamauchi, Yoshito Nakazawa, Yuji Yatsuda
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Patent number: 5519244Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.Type: GrantFiled: July 6, 1994Date of Patent: May 21, 1996Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Takaaki Hagiwara, Ryuji Kondo, Shinichi Minami, Yokichi Itoh
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Patent number: 5348898Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.Type: GrantFiled: January 26, 1993Date of Patent: September 20, 1994Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Takaaki Hagiwara, Ryuji Kondo, Shinichi Minami, Yokichi Itoh
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Patent number: 5252505Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.Type: GrantFiled: January 15, 1992Date of Patent: October 12, 1993Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Takaaki Hagiwara, Ryuji Kondo, Shinichi Minami, Yokichi Itoh
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Patent number: 5177584Abstract: A bipolar SRAM which includes a forward bipolar transistor and a reverse bipolar transistor on an identical semiconductor substrate, is disclosed. Concretely, the base region of the reverse bipolar transistor is formed at a deeper position of the substrate than the base region of the forward bipolar transistor, thereby to heighten the cutoff frequency f.sub.T of the reverse bipolar transistor.Type: GrantFiled: January 28, 1991Date of Patent: January 5, 1993Assignee: Hitachi, Ltd.Inventors: Akihisa Uchida, Yuji Yatsuda, Katsumi Ogiue, Kazuo Nakazato, Takahiro Onai
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Patent number: 5114870Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.Type: GrantFiled: May 15, 1989Date of Patent: May 19, 1992Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Takaaki Hagiwara, Ryuji Kondo, Shinichi Minami, Yokichi Itoh
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Patent number: 5057445Abstract: In a semiconductor device comprising a plurality of planar high-voltage insulated-gate field-effect transistors in which offset regions are provided in portions of the semiconductor substrate near the junctions of the adjacent drain regions and near the substrate surface, low impurity concentration offset regions are formed in the semiconductor substrate in such a manner that each low impurity concentration offset region is coupled the source region and is located between the drain regions of the field-effect transistors adjacent to each other and near the semiconductor surface, whereby reduction of the "on resistance" is achieved without affecting the FET sustaining voltage.Type: GrantFiled: January 11, 1991Date of Patent: October 15, 1991Assignee: Kyocera CorporationInventors: Ching F. Yeh, Yuji Yatsuda
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Patent number: 4989224Abstract: A coincidence circuit for detecting when n-bit binary input data coincides with the current value of an n-bit counter. A plurality of "1" detecting circuits determine, when a corresponding input bit is one, whether a corresponding counter bit is also one. A first-coincidence detecting circuit determines the first time that all the "1" input bits have corresponding "1" clock bits. Each "1" detecting circuit includes an inverter and a NOR gate. The first-coincidence detecting circuit includes an OR gate and a latch circuit.Type: GrantFiled: November 29, 1988Date of Patent: January 29, 1991Assignee: Fuji Xerox Co., Ltd.Inventors: Mitsumasa Narahara, Kazumi Yamauchi, Yuji Yatsuda, Shinichi Yasunaga, Fujio Moriguchi, Nobuhisa Kato
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Patent number: 4961101Abstract: In a semiconductor device comprising a plurality of planar high-voltage insulated-gate field-effect transistors in which offset regions are provided in portions of the semiconductor substrate near the junctions of adjacent drain regions and near the substrate surface additional, low impurity concentration offset regions are formed in the semiconductor substrate in such a manner that each low impurity concentration offset region is coupled to a source region and is located between the drain regions of the field-effect transistors adjacent to each other and near the semiconductor surface, whereby reduction of the "on resistance" is achieved without affecting the FET sustaining voltage.Type: GrantFiled: April 20, 1988Date of Patent: October 2, 1990Assignee: Fuji Xerox Co., Ltd.Inventors: Ching Fa Yeh, Yuji Yatsuda
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Patent number: 4851364Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.Type: GrantFiled: April 10, 1986Date of Patent: July 25, 1989Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Takaaki Hagiwara, Ryuji Kondo, Shinichi Minami, Yokichi Itoh
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Method of manufacturing an integrated CMOS of ordinary logic circuit and of high voltage MOS circuit
Patent number: 4818719Abstract: A method of manufacturing a semiconductor device having a high voltage CMOS unit for an ordinary logic operation and a MOS unit which are provided in a single semiconductor substrate of a first conduction type. The method includes the steps of performing an element region making process for making a well of a second conduction type in the substrate, performing a process for providing field-effect transistors having channels of mutually different conduction types in the substrate and the well, and then performing a process for providing electrode wiring layers. Finally, a process is performed for providing a first impurity region having a particular conduction type and serving as a channel stopper of the CMOS unit and a second impurity region having the conduction type of the first impurity region and serving as an offset low-resistance layer of the high voltage MOS unit.Type: GrantFiled: July 16, 1987Date of Patent: April 4, 1989Assignee: Fuji Xerox Co., Ltd.Inventors: Ching-Fa Yeh, Yasunao Misawa, Yuji Yatsuda -
Patent number: 4668970Abstract: In a semiconductor device which includes an insulation film through which a charge can tunnel, a gate insulation film of a material different from the material of said insulation film or having a thickness different from that of said insulation film, and a floating gate extending over said tunnelable insulation film, the improvement wherein at least two sides of said tunnelable region are bounded by a device separation oxide film.Type: GrantFiled: December 2, 1985Date of Patent: May 26, 1987Assignee: Hitachi, Ltd.Inventors: Yuji Yatsuda, Takaaki Hagiwara, Masatada Horiuchi, Shinichi Minami, Toru Kaga
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Patent number: 4654828Abstract: A semiconductor nonvolatile memory wherein a unit cell is constructed of a series connection consisting of an MNOS (metal-silicon nitride-silicon dioxide-semiconductor) transistor whose gate electrode is made of polycrystalline silicon and an MOS (metal-silicon dioxide-semiconductor) transistor whose gate electrode is also made of polycrystalline silicon, such unit cells being arrayed in the form of a matrix, and wherein the gate electrode of the MOS transistor is used as a reading word line, the gate electrode of the MNOS transistor is used as a writing word line, and a terminal of either of the MNOS transistor and the MOS transistor connected in series and constituting the unit cell is used as a data line.Type: GrantFiled: October 15, 1985Date of Patent: March 31, 1987Assignee: Hitachi, Ltd.Inventors: Takaaki Hagiwara, Yokichi Itoh, Ryuji Kondo, Yuji Yatsuda, Shinichi Minami
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Patent number: 4653025Abstract: A static RAM having a plurality of memory cells. Each memory cell consists of driver MOST's that are connected to each other in a crossing manner, and transfer MOST's that connect storage nodes of the memory cell to the data lines. The driver MOST's are comprised of n-channel MOST's, and the transfer MOST's are comprised of p-channel MOST's.Type: GrantFiled: December 21, 1984Date of Patent: March 24, 1987Assignee: Hitachi, Ltd.Inventors: Osamu Minato, Masakazu Aoki, Yuji Yatsuda, Katsuaki Takagi, Masashi Horiguchi