Abstract: A semiconductor structure for a memory device includes a substrate including a memory cell region and a peripheral circuit region defined thereon, at least an active region formed in the peripheral circuit region, a buried gate structure formed in the active region in the peripheral circuit region, a conductive line structure formed on the buried gate structure, and at least a bit line contact plug formed in the memory cell region.

Abstract: The present disclosure provides a semiconductor device and a method of fabricating the same, which includes a substrate, a resistor structure, a bit line structure, and a bit line contact. The substrate has an active area and a plurality of isolating regions. The resistor structure is disposed on the isolating regions, and includes a first semiconductor layer, a first capping layer, a first spacer. The bit line structure is disposed on the substrate to intersect the active area and the isolating regions, and includes a second semiconductor layer, a first conductive layer, a second capping layer, and a second spacer. The bit line contact is disposed in the substrate to partially extend into the second semiconductor layer, wherein the bit line contact and the first semiconductor layer include a same semiconductor material.

Abstract: The present disclosure provides a semiconductor memory device and a fabricating method thereof, which includes a substrate, a bit line structure and a resistor structure. The substrate has a plurality of active areas and an isolating region. The resistor structure includes a first semiconductor layer and a first capping layer from bottom to top. The bit line structure includes a second semiconductor layer, a first conductive layer, and a second capping layer from bottom to top, wherein the first semiconductor layer and the second semiconductor layer include coplanar top surface and a same semiconductor material. In this way, the resistor formed thereby is allowable to obtain structural reliability and stable surface resistance, under a simplified process flow.

Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, and which includes a substrate, bit lines, bit line contacts, a gate structure, a first oxidized interface layer, and a second oxidized interface layer. The bit lines are disposed on the substrate, and the bit line contacts are disposed below the bit lines. The gate structure is disposed on the substrate, wherein each bit line and the gate structure respectively include a semiconductor layer, a conductive layer, and a covering layer stacked from bottom to top. The first oxidized interface layer is disposed between each bit line contact and the semiconductor layer of each bit line. The second oxidized interface layer is disposed within the semiconductor layer of the gate structure, wherein a topmost surface of the first oxidized interface layer is higher than a topmost surface of the second oxidized interface layer.

Abstract: A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, and isolation structures. The bit line structures, the storage node contacts, and the isolation structures are disposed on the semiconductor substrate. Each bit line structure is elongated in a first direction, and the bit line structures are repeatedly disposed in a second direction. Each storage node contact and each isolation structure are disposed between two of the bit line structures adjacent to each other in the second direction. Each storage node contact is disposed between two of the isolation structures disposed adjacent to each other in the first direction. Each isolation structure includes at least one first portion elongated in the first direction and partially disposed between one of the bit line structures and one of the storage node contacts adjacent to the isolation structure in the second direction.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and first fuse branches and second fuse branches are formed in the substrate, in which the first fuse branches and the second fuse branches are separated by a shallow trench isolation (STI) and the second fuse branches include different sizes. Next, fuse elements are formed to connect the first fuse branches and the second fuse branches.

Abstract: A semiconductor structure for a memory device includes a substrate including a memory cell region and a peripheral circuit region defined thereon, at least an active region formed in the peripheral circuit region, a buried gate structure formed in the active region in the peripheral circuit region, a conductive line structure formed on the buried gate structure, and at least a bit line contact plug formed in the memory cell region.

Abstract: A resistor for dynamic random access memory includes a substrate with a memory cell region and a peripheral region defined thereon, and a resistor formed on a shallow trench isolation of the substrate, wherein the resistor is provided with a winding portion and terminal portions at two ends of the winding portion. The winding portion is electrically connected with an overlying metal layer through contacts, and the terminal portion includes a polysilicon layer and a metal multilayer from the bottom up.

Abstract: A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, and isolation structures. The bit line structures, the storage node contacts, and the isolation structures are disposed on the semiconductor substrate. Each bit line structure is elongated in a first direction, and the bit line structures are repeatedly disposed in a second direction. Each storage node contact and each isolation structure are disposed between two of the bit line structures adjacent to each other in the second direction. Each storage node contact is disposed between two of the isolation structures disposed adjacent to each other in the first direction. Each isolation structure includes at least one first portion elongated in the first direction and partially disposed between one of the bit line structures and one of the storage node contacts adjacent to the isolation structure in the second direction.

Abstract: A semiconductor device includes a shallow trench isolation (STI) in a substrate and a first gate structure on the STI. Preferably, the first gate structure comprises a first horizontal portion on the STI, a vertical portion connected to the first horizontal portion and extended into part of the STI, and a second horizontal portion connected to the vertical portion. The semiconductor device further includes a first spacer on a sidewall of the first gate structure and the STI and a second spacer on another sidewall of the first gate structure and on the second horizontal portion.

Abstract: A semiconductor device includes a shallow trench isolation (STI) in a substrate and a first gate structure on the STI. Preferably, the first gate structure comprises a first horizontal portion on the STI, a vertical portion connected to the first horizontal portion and extended into part of the STI, and a second horizontal portion connected to the vertical portion. The semiconductor device further includes a first spacer on a sidewall of the first gate structure and the STI and a second spacer on another sidewall of the first gate structure and on the second horizontal portion.

Abstract: A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, and isolation structures. The bit line structures, the storage node contacts, and the isolation structures are disposed on the semiconductor substrate. Each bit line structure is elongated in a first direction, and the bit line structures are repeatedly disposed in a second direction. Each storage node contact and each isolation structure are disposed between two of the bit line structures adjacent to each other in the second direction. Each storage node contact is disposed between two of the isolation structures disposed adjacent to each other in the first direction. Each isolation structure includes at least one first portion elongated in the first direction and partially disposed between one of the bit line structures and one of the storage node contacts adjacent to the isolation structure in the second direction.

Abstract: A semiconductor device includes a substrate having a cell region and a peripheral region, a thyristor on the cell region, a MOS transistor on the peripheral region, and a first silicide layer on the substrate adjacent to the thyristor on the cell region. Preferably, the thyristor includes: a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the cell region, vertical dielectric patterns in the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer, and first contact plugs on the fourth semiconductor layer.

Abstract: A DRAM device with embedded flash memory for redundancy is disclosed. The DRAM device includes a substrate having a DRAM array area and a peripheral area. The peripheral area includes an embedded flash forming region and a first transistor forming region. DRAM cells are disposed within the DRAM array area. Flash memory is disposed in the embedded flash forming region. The flash memory includes an ONO storage structure and a flash memory gate structure. A first transistor is disposed in the first transistor forming region.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first trench isolation is formed in a substrate. A second trench isolation is formed in the substrate after the step of forming the first trench isolation. The second trench isolation is formed at a side of the first trench isolation, and the second trench isolation is directly connected with the first trench isolation. The semiconductor structure includes the substrate, the first trench isolation, and the second trench isolation. A material of the second trench isolation is different from a material of the first trench isolation. The first trench isolation is disposed at one side of the second trench isolation, and the second trench isolation is directly connected with the first trench isolation.

Abstract: A fuse structure for dynamic random access memory (DRAM) includes: a shallow trench isolation (STI) in a substrate; a first select gate in the substrate and adjacent to one side of the STI; a second select gate in the substrate and adjacent to another side of the STI; and a gate structure on the STI, the first select gate, and the second select gate.

Abstract: A semiconductor substrate of first conductivity type is provided. At least one active area is formed on the semiconductor substrate. A major axis of the active area extends along a first direction. A first oblique ion implantation process is performed to form a first doped region of second conductivity type above a first depth on an end surface of the active area. A second oblique ion implantation process is performed to form a second doped region of third conductivity type above a second depth on the end surface of the active area. The third conductivity type and the second conductivity types are opposite to each other, so that a localized doped region having the second conductivity type is formed between the first depth and the second depth. A trench isolation structure is formed around the active area and adjacent to the end surface of the active area.

Abstract: A layout of a sense amplifier includes a pre-charge and equalizer area. A pre-charge transistor, an equalizer transistor and a gate line are disposed within the pre-charge and equalizer area. The gate line and the pre-charge transistor share a share plug. The share plug serves as a gate contact plug for the gate line and a source/drain contact plug for the pre-charge transistor.

Abstract: A layout of a sense amplifier includes a pre-charge and equalizer area. A pre-charge transistor, an equalizer transistor and a gate line are disposed within the pre-charge and equalizer area. The gate line and the pre-charge transistor share a share plug. The share plug serves as a gate contact plug for the gate line and a source/drain contact plug for the pre-charge transistor.

Abstract: A DRAM device with embedded flash memory for redundancy is disclosed. The DRAM device includes a substrate having a DRAM array area and a peripheral area. The peripheral area includes an embedded flash forming region and a first transistor forming region. DRAM cells are disposed within the DRAM array area. Flash memory is disposed in the embedded flash forming region. The flash memory includes an ONO storage structure and a flash memory gate structure. A first transistor is disposed in the first transistor forming region.