Abstract: A semiconductor device includes: a substrate having a base and a pillar array including a plurality of pillars; a plurality of bit lines, each of which is disposed between two adjacent ones of the columns of the pillar array; a plurality of word lines, each of which is connected to a corresponding one of the rows of the pillar array; and a contact array including a plurality of bit line contacts arranged in rows and columns. The bit line contacts of each column of the contact array are embedded in the base and are electrically connected to a respective one of the bit lines. Each bit line contact intersects the respective one of the bit lines and extends between and is electrically connected to two adjacent ones of the pillars.

Abstract: A semiconductor device includes: a substrate having a base and a pillar array including a plurality of pillars; a plurality of bit lines, each of which is disposed between two adjacent ones of the columns of the pillar array; a plurality of word lines, each of which is connected to a corresponding one of the rows of the pillar array; and a contact array including a plurality of bit line contacts arranged in rows and columns. The bit line contacts of each column of the contact array are embedded in the base and are electrically connected to a respective one of the bit lines. Each bit line contact intersects the respective one of the bit lines and extends between and is electrically connected to two adjacent ones of the pillars.

Abstract: A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.

Abstract: A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.

Abstract: A vertical transistor structure comprises a substrate, a plurality of pillars formed on the substrate and spaced from each other, a plurality of trenches each formed between two adjacent pillars, a protection layer formed on the surface of a first side wall and the surface of a second side wall of the trench, a first gate and a second gate respectively formed on the protection layer of the first side wall and the second side wall, and a separation layer covering a bottom wall of the trench. The present invention uses the separation layer functioning as an etch stopping layer to the first gate and the second gate while being etched. Further, thickness of the separation layer is used to control the distance between the bottom wall and the first and second gates and define widths of the drain and the source formed in the pillar via ion implantation.

Abstract: A vertical transistor structure includes a substrate, a plurality of pillars located on the substrate and spaced from each other at a selected distance, a gate line and a plurality of conductors. The pillars are aligned in a straight line in a first direction and have respectively a primary control wall along the first direction and two ancillary control walls perpendicular to the primary control wall. The gate line is connected to the primary control wall in the first direction through a first isolated layer. The conductors are interposed between the ancillary control walls through second isolated layers. By providing the gate line merely on the primary control wall and the conductors to aid the gate line to control ON/OFF of the pillars, problems of etching and separating gate material during gradually shrunken feature size process that are difficult to control etching positions and etching duration can be prevented.

Abstract: A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.

Abstract: A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.

Abstract: A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.

Abstract: A vertical channel transistor array includes a plurality of embedded bit lines, a plurality of bit line contacts, a plurality of embedded word lines, and a current leakage isolation structure. An active area of a vertical channel transistor is defined by the semiconductor pillars. The embedded bit lines are disposed in parallel in a semiconductor substrate and extended in a column direction. Each of the bit line contacts is respectively disposed at a side of one of the embedded bit lines. The embedded word lines are disposed in parallel above the embedded bit lines and extended in a row direction. Besides, the embedded word lines and the semiconductor pillars in the same row are connected but spaced by a gate dielectric layer. The current leakage isolation structure is disposed at ends of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.

Abstract: A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.

Abstract: A method for manufacturing a capacitor bottom electrode of a dynamic random access memory is provided. The method comprises providing a substrate having a memory cell region and forming a polysilicon template layer on the memory cell region of the substrate. A supporting layer is formed on the polysilicon template layer and plural openings penetrating through the supporting layer and the polysilicon template layer are formed and a liner layer is formed on at least a portion of the polysilicon template layer exposed by the openings A conductive layer substantially conformal to the substrate is formed on the substrate. A portion of the conductive layer on the supporting layer is removed so as to form plural capacitor bottom electrodes. Using the polysilicon template layer, the openings with relatively better profiles are formed and the dimension of the device can be decreased.

Abstract: In a semiconductor device, an active region is formed in a semiconductor substrate separated by a plurality of isolation regions. A plurality of surface insulating films of different thickness are formed separately on the active region. A plurality of conductive films are formed on the respective insulating films. Then, one of the surface insulating film having smaller thickness is caused to break down to work as an electric fuse.

Abstract: There is described a semiconductor device having a storage node capacitor structure suitable for rendering memory cells compact, and storage nodes are prevented from tilting. The device includes a storage node which has a vertical surface extending in the direction perpendicular to the surface of a semiconductor substrate, and a dielectric film for tilt prevention purposes which is brought into close contact with the side surface of the vertical surface and which prevents the vertical surface from tilting.

Abstract: A semiconductor device having a test mark comprising: a semiconductor substrate; a first TEOS layer formed on the semiconductor substrate; a second TEOS layer formed on the first TEOS layer and having a fluidity lower than that of the first TEOS layer at an elevated temperature; a recess formed in the first and second TEOS layers and exposing the surface of the semiconductor substrate, wherein the horizontal cross section of the recess is substantially rectangular in configuration; and a metal layer formed between the first and second TEOS layers and opposing to the corner of the recess.

Abstract: There is described a semiconductor device having a storage node capacitor structure suitable for rendering memory cells compact, and storage nodes are prevented from tilting. The device includes a storage node which has a vertical surface extending in the direction perpendicular to the surface of a semiconductor substrate, and a dielectric film for tilt prevention purposes which is brought into close contact with the side surface of the vertical surface and which prevents the vertical surface from tilting.

Abstract: A semiconductor device with capacitors which have a structure wherein fluctuation in thickness does not occur, even in the case that a dielectric film of low coverage is used. The semiconductor device is provided with adjoining first and second capacitors, wherein the respective capacitor is provided with lower electrode, dielectric film which contacts the top surface of the lower electrode and which has peripheral sidewall surfaces that continue to the peripheral sidewall surfaces of the lower electrode, first upper electrode that contacts the top surface of the dielectric film and a second upper electrode that contacts the top surface of the first upper electrode and the semiconductor device is further provided with a partition insulating film which covers the sidewall surfaces of lower electrode and the dielectric layer between the capacitors so that the second upper electrode contacts the top surface of the partition insulating film.

Abstract: Storage node plugs are formed on a semiconductor substrate. A silicon nitride film is formed on a silicon oxide film. By etching the silicon oxide film with the silicon nitride film as a mask, storage node openings each exposing a surface of a corresponding storage node plug are formed, followed by forming a capacitor including a storage node, a capacitor dielectric film and a cell plate in a corresponding opening. With such a procedure, there can be obtained a semiconductor device in which electric short-circuit between adjacent elements is prevented from occurring; and a manufacturing method of such a semiconductor device.

Abstract: A method of manufacturing semiconductor device is provided which can minimize the thinning of a nitride layer in the planarization process and inhibit the peripheral area of the nitride layer from being excessively polished. The method of manufacturing semiconductor device includes the steps of: forming a nitride layer on a semiconductor substrate; patterning the nitride layer and etching the semiconductor substrate while masking with a pattern of the nitride layer to form a trench; depositing an oxide layer to fill the trench and cover the nitride layer; patterning a resist layer on the oxide layer; etching the oxide layer on the nitride layer; and planarizing the oxide layer, wherein the step of etching the oxide layer permits a thickness of the oxide layer to be left on the nitride layer.

Abstract: A semiconductor device with capacitors which have a structure wherein fluctuation in thickness does not occur, even in the case that a dielectric film of low coverage is used. The semiconductor device is provided with adjoining first and second capacitors, wherein the respective capacitor is provided with lower electrode, dielectric film which contacts the top surface of the lower electrode and which has peripheral sidewall surfaces that continue to the peripheral sidewall surfaces of the lower electrode, first upper electrode that contacts the top surface of the dielectric film and a second upper electrode that contacts the top surface of the first upper electrode and the semiconductor device is further provided with a partition insulating film which covers the sidewall surfaces of lower electrode and the dielectric layer between the capacitors so that the second upper electrode contacts the top surface of the partition insulating film.