Patents by Inventor Yukio Nakabayashi

Yukio Nakabayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10714610
    Abstract: A semiconductor device of an embodiment includes a silicon carbide layer; a gate electrode; a gate insulating layer disposed between the silicon carbide layer and the gate electrode; a first region disposed in the silicon carbide layer and containing nitrogen (N); and a second region disposed between the first region and the gate insulating layer, and containing at least one element selected from the group consisting of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), scandium (Sc), yttrium (Y), lanthanum (La), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu), hydrogen (H), deuterium (D), and fluorine (F).
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 14, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Ryosuke Iijima, Toshihide Ito, Shunsuke Asaba, Yukio Nakabayashi, Shigeto Fukatsu
  • Publication number: 20200161886
    Abstract: A power feed unit according to an embodiment of the present disclosure includes two or more first terminal sections, a second terminal section, and a switch. The first terminal sections each include a first power supply terminal directed to receiving electric power from the battery, and a first communication terminal directed to performing communication with the battery. The second terminal section includes a second power supply terminal directed to supplying electric power to the electronic apparatus, and a second communication terminal directed to performing communication with the electronic apparatus. The switch electrically couples one first communication terminal of the two or more first communication terminals and the second communication terminal to each other.
    Type: Application
    Filed: March 5, 2018
    Publication date: May 21, 2020
    Inventors: Nobutaka Saitoh, Yukio Tsuchiya, Toshiya Nakabayashi
  • Patent number: 10526722
    Abstract: The present invention provides a method of manufacturing by the sublimation-recrystallization method more accurately detecting a thermal state of a starting material in a crucible and enabling control of the growth conditions while manufacturing an SiC single crystal.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: January 7, 2020
    Assignee: SHOWA DENKO K.K.
    Inventors: Masashi Nakabayashi, Kiyoshi Kojima, Hiroyuki Deai, Kota Shimomura, Yukio Nagahata
  • Publication number: 20190296146
    Abstract: A semiconductor device of an embodiment includes a silicon carbide layer; a gate electrode; a gate insulating layer disposed between the silicon carbide layer and the gate electrode; a first region disposed in the silicon carbide layer and containing nitrogen (N); and a second region disposed between the first region and the gate insulating layer, and containing at least one element selected from the group consisting of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), scandium (Sc), yttrium (Y), lanthanum (La), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu), hydrogen (H), deuterium (D), and fluorine (F).
    Type: Application
    Filed: August 27, 2018
    Publication date: September 26, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Ryosuke IIJIMA, Toshihide ITO, Shunsuke ASABA, Yukio NAKABAYASHI, Shigeto FUKATSU
  • Publication number: 20180330949
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include performing a first heat treatment of a first film at a first temperature not less than 500° C. and not more than 900° C. in a first atmosphere including oxygen. The first film includes silicon and oxygen and is deposited on a semiconductor member including silicon carbide. The method can include performing, after the first heat treatment, a second heat treatment of the first film at a second temperature not less than 1200° C. but less than 1400° C. in a second atmosphere including nitrogen.
    Type: Application
    Filed: February 12, 2018
    Publication date: November 15, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shunsuke ASABA, Ryosuke IIJIMA, Yukio NAKABAYASHI, Shigeto FUKATSU, Toshihide ITO
  • Patent number: 9755055
    Abstract: A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: September 5, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masumi Saitoh, Toshinori Numata, Yukio Nakabayashi
  • Patent number: 9048251
    Abstract: The semiconductor device of this embodiment includes: a first region of a first conductivity type SiC; a second region of a first conductivity type SiC, impurity concentration of first conductivity type of the second region being lower than impurity concentration of first conductivity type of the first region; a third region of a second conductivity type SiC provided between the first region and the second region; a Si layer provided on surfaces of the first, second, and third regions, a thickness of the Si layer on the third region being thicker than a thickness of the Si layer on the second region; a gate insulating film provided on the Si layer; and a date electrode provided on the gate insulating film.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: June 2, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryosuke Iijima, Yukio Nakabayashi, Tatsuo Shimizu
  • Patent number: 9041008
    Abstract: A semiconductor device of an embodiment includes a first conductive type silicon carbide substrate having first and second main surfaces, a first conductive type silicon carbide layer formed on the first main surface, a second conductive type first silicon carbide region formed in the silicon carbide layer, and a first conductive type second silicon carbide region formed in the first silicon carbide region. The device includes a trench penetrating through the first and second silicon carbide regions, and a second conductive type third silicon carbide region formed on a bottom and a side surface of the trench. The third silicon carbide region is in contact with the first silicon carbide region, and is formed between the trench and the silicon carbide layer. In addition, the device includes a gate insulating film formed in the trench, a gate electrode, a first electrode, and a second electrode.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukio Nakabayashi, Takashi Shinohe, Atsuko Yamashita
  • Patent number: 9018636
    Abstract: According to one embodiment, a semiconductor device includes a first and a second transistor. The first transistor includes a first and a second region of a first conductivity type and a third region of a second conductivity type. The first region is disposed along a first crystal face of a silicon carbide region. The silicon carbide region has the first crystal face and a second crystal face. The second and the third region are disposed along the first face. The third region is provided between the first and the second region. The second transistor includes a fourth and fifth region of the second type and a sixth region of the first type. The fourth, the fifth and the sixth region are disposed along the second face of the silicon carbide region. The sixth region is provided between the fourth and the fifth region.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: April 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryosuke Iijima, Yukio Nakabayashi, Takashi Shinohe
  • Publication number: 20150097189
    Abstract: A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.
    Type: Application
    Filed: December 12, 2014
    Publication date: April 9, 2015
    Inventors: Masumi Saitoh, Toshinori Numata, Yukio Nakabayashi
  • Publication number: 20150084067
    Abstract: The semiconductor device of this embodiment includes: a first region of a first conductivity type SiC; a second region of a first conductivity type SiC, impurity concentration of first conductivity type of the second region being lower than impurity concentration of first conductivity type of the first region; a third region of a second conductivity type SiC provided between the first region and the second region; a Si layer provided on surfaces of the first, second, and third regions, a thickness of-the Si layer on the third region being thicker than a thickness of the Si layer on the second region; a gate insulating film provided on the Si layer; and a date electrode provided on the gate insulating film.
    Type: Application
    Filed: August 13, 2014
    Publication date: March 26, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ryosuke IIJIMA, Yukio NAKABAYASHI, Tatsuo SHIMIZU
  • Publication number: 20150076523
    Abstract: According to one embodiment, a semiconductor device includes a first and a second transistor. The first transistor includes a first and a second region of a first conductivity type and a third region of a second conductivity type. The first region is disposed along a first crystal face of a silicon carbide region. The silicon carbide region has the first crystal face and a second crystal face. The second and the third region are disposed along the first face. The third region is provided between the first and the second region. The second transistor includes a fourth and fifth region of the second type and a sixth region of the first type. The fourth, the fifth and the sixth region are disposed along the second face of the silicon carbide region. The sixth region is provided between the fourth and the fifth region.
    Type: Application
    Filed: November 24, 2014
    Publication date: March 19, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ryosuke IIJIMA, Yukio Nakabayashi, Takashi Shinohe
  • Patent number: 8932915
    Abstract: A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: January 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masumi Saitoh, Toshinori Numata, Yukio Nakabayashi
  • Patent number: 8669162
    Abstract: A method of manufacturing a semiconductor device according to an embodiment includes: forming a plurality of semiconductor layers located at a distance from one another on a first insulating film; forming a gate insulating film that covers both side faces and an upper face of each of the semiconductor layers; forming a gate electrode of a polysilicon film to cover the gate insulating film of each of the semiconductor layers; forming a second insulating film on an entire surface; exposing an upper face of the gate electrode by performing selective etching on a portion of the second insulating film; siliciding the gate electrode; and forming a stress applying film that applies a stress in a direction perpendicular to the extending direction of each of the semiconductor layers and parallel to an upper face of the first insulating film.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: March 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukio Nakabayashi, Toshinori Numata
  • Patent number: 8569795
    Abstract: A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon ca
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: October 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kono, Yukio Nakabayashi, Takashi Shinohe, Makoto Mizukami
  • Patent number: 8492219
    Abstract: In a semiconductor device manufacturing method, a first semiconductor region which includes a narrow portion and a wide portion is formed in an upper portion of a semiconductor substrate, a gate insulating film is formed on at least side surfaces of the narrow portion, a gate electrode is formed on the gate insulating film, a mask pattern that covers the wide portion is formed, ion implantation of an impurity is performed with the mask pattern as a mask to form an extension impurity region in the narrow portion, the mask pattern is removed, a heat treatment is performed to activate the impurity, a gate sidewall is formed on a side surface of the gate electrode, epitaxial growth of a semiconductor film is performed on the narrow portion and the wide portion after the formation of the gate sidewall, and source-drain regions is formed on both sides of the gate electrode.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: July 23, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masumi Saitoh, Toshinori Numata, Yukio Nakabayashi
  • Patent number: 8467241
    Abstract: In a semiconductor layer, information is written by applying a first potential to a first electrode, applying a second potential that is lower than the first potential to all of back gate electrodes, applying a third potential that is higher than the first potential to the first to (i?1)th front gate electrodes, and applying a fourth potential that is between the second and third potentials to the ith and subsequent front gate electrodes, where “i” is a positive integer and identifies a specific location to which information is to be written.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: June 18, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun Fujiki, Kiwamu Sakuma, Naoki Yasuda, Yukio Nakabayashi, Masumi Saitoh
  • Publication number: 20120282743
    Abstract: In a semiconductor device manufacturing method, a first semiconductor region which includes a narrow portion and a wide portion is formed in an upper portion of a semiconductor substrate, a gate insulating film is formed on at least side surfaces of the narrow portion, a gate electrode is formed on the gate insulating film, a mask pattern that covers the wide portion is formed, ion implantation of an impurity is performed with the mask pattern as a mask to form an extension impurity region in the narrow portion, the mask pattern is removed, a heat treatment is performed to activate the impurity, a gate sidewall is formed on a side surface of the gate electrode, epitaxial growth of a semiconductor film is performed on the narrow portion and the wide portion after the formation of the gate sidewall, and source-drain regions is formed on both sides of the gate electrode.
    Type: Application
    Filed: June 4, 2012
    Publication date: November 8, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masumi SAITOH, Toshinori Numata, Yukio Nakabayashi
  • Publication number: 20120228637
    Abstract: A semiconductor device of an embodiment includes a first conductive type silicon carbide substrate having first and second main surfaces, a first conductive type silicon carbide layer formed on the first main surface, a second conductive type first silicon carbide region formed in the silicon carbide layer, and a first conductive type second silicon carbide region formed in the first silicon carbide region. The device includes a trench penetrating through the first and second silicon carbide regions, and a second conductive type third silicon carbide region formed on a bottom and a side surface of the trench. The third silicon carbide region is in contact with the first silicon carbide region, and is formed between the trench and the silicon carbide layer. In addition, the device includes a gate insulating film formed in the trench, a gate electrode, a first electrode, and a second electrode.
    Type: Application
    Filed: March 5, 2012
    Publication date: September 13, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: YUKIO NAKABAYASHI, TAKASHI SHINOHE, ATSUKO YAMASHITA
  • Publication number: 20120228631
    Abstract: A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon ca
    Type: Application
    Filed: August 25, 2011
    Publication date: September 13, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi KONO, Yukio Nakabayashi, Takashi Shinohe, Makoto Mizukami