Patents by Inventor Yukio Nakabayashi
Yukio Nakabayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120146114Abstract: A method of manufacturing a semiconductor device according to an embodiment includes: forming a plurality of semiconductor layers located at a distance from one another on a first insulating film; forming a gate insulating film that covers both side faces and an upper face of each of the semiconductor layers; forming a gate electrode of a polysilicon film to cover the gate insulating film of each of the semiconductor layers; forming a second insulating film on an entire surface; exposing an upper face of the gate electrode by performing selective etching on a portion of the second insulating film; siliciding the gate electrode; and forming a stress applying film that applies a stress in a direction perpendicular to the extending direction of each of the semiconductor layers and parallel to an upper face of the first insulating film.Type: ApplicationFiled: February 21, 2012Publication date: June 14, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yukio NAKABAYASHI, Toshinori Numata
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Publication number: 20120146053Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, first gate sidewalls formed on both sides of the gate electrode, and a source/drain semiconductor layer formed on the semiconductor substrate to sandwich the first gate sidewalls with the gate electrode. Further, second gate sidewalls are provided on the first gate sidewalls and the source/drain semiconductor layer at both sides of the gate electrode, wherein the boundary of each of the second gate sidewalls with each of the first gate sidewalls is terminated at the side surface of the gate electrode, and each of the second gate sidewalls has a smaller Young's modulus and a lower dielectric constant than each of the first gate sidewalls.Type: ApplicationFiled: September 20, 2011Publication date: June 14, 2012Inventors: Masumi SAITOH, Toshinori Numata, Yukio Nakabayashi, Kensuke Ota
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Publication number: 20120075928Abstract: In a semiconductor layer, information is written by applying a first potential to a first electrode, applying a second potential that is lower than the first potential to all of back gate electrodes, applying a third potential that is higher than the first potential to the first to (i?1)th front gate electrodes, and applying a fourth potential that is between the second and third potentials to the ith and subsequent front gate electrodes, where “i” is a positive integer and identifies a specific location to which information is to be written.Type: ApplicationFiled: September 28, 2011Publication date: March 29, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Jun Fujiki, Kiwamu Sakuma, Naoki Yasuda, Yukio Nakabayashi, Masumi Saitoh
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Publication number: 20110303972Abstract: A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.Type: ApplicationFiled: April 7, 2011Publication date: December 15, 2011Inventors: Masumi SAITOH, Toshinori Numata, Yukio Nakabayashi
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Patent number: 7781274Abstract: A multi-gate field effect transistor includes: a plurality of semiconductor layers arranged in parallel on a substrate; source and drain regions formed in each of the semiconductor layers; channel regions each provided between the source region and the drain region in each of the semiconductor layers; protection films each provided on an upper face of each of the channel regions; gate insulating films each provided on both side faces of each of the channel regions; a plurality of gate electrodes provided on both side faces of each of the channel regions so as to interpose the gate insulating film, provided above the upper face of each of the channel region so as to interpose the protection film, and containing a metal element; a connecting portion connecting upper faces of the gate electrodes; and a gate wire connected to the connecting portion.Type: GrantFiled: September 15, 2008Date of Patent: August 24, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yukio Nakabayashi, Ken Uchida
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Publication number: 20090242986Abstract: A multi-gate field effect transistor includes: a plurality of semiconductor layers arranged in parallel on a substrate; source and drain regions formed in each of the semiconductor layers; channel regions each provided between the source region and the drain region in each of the semiconductor layers; protection films each provided on an upper face of each of the channel regions; gate insulating films each provided on both side faces of each of the channel regions; a plurality of gate electrodes provided on both side faces of each of the channel regions so as to interpose the gate insulating film, provided above the upper face of each of the channel region so as to interpose the protection film, and containing a metal element; a connecting portion connecting upper faces of the gate electrodes; and a gate wire connected to the connecting portion.Type: ApplicationFiled: September 15, 2008Publication date: October 1, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yukio NAKABAYASHI, Ken UCHIDA
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Patent number: 7521752Abstract: It is possible to reliably implant an impurity into an impurity forming region, and to form a self-aligned silicides on the entire portion of the source and drain regions.Type: GrantFiled: March 21, 2006Date of Patent: April 21, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Atsuhiro Kinoshita, Junji Koga, Yukio Nakabayashi
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Patent number: 7479674Abstract: An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.Type: GrantFiled: February 21, 2008Date of Patent: January 20, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Yukio Nakabayashi, Kazumi Nishinohara, Atsuhiro Kinoshita, Junji Koga
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Publication number: 20080237655Abstract: A semiconductor apparatus includes: a support substrate made of a semiconductor; an insulating layer provided on the support substrate and having a first and a second openings; a semiconductor fin having a channel section, a first and second buried regions, a source section and a drain section; a gate insulating film covering a side face of the channel section; and a gate electrode opposed to the side face of the channel section across the gate insulating film. The channel section is provided upright on the insulating layer between the first and the second openings. The first and the second buried regions are provided in the first and the second openings on both sides of the channel section. The source-drain sections are provided on the first and the second buried regions and connected to the channel section.Type: ApplicationFiled: March 24, 2008Publication date: October 2, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yukio NAKABAYASHI, Atsuhiro Kinoshita, Junji Koga
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Publication number: 20080227241Abstract: A semiconductor device fabrication method for forming on a wafer-bonded substrate p- and n-type FinFETs each having a channel plane exhibiting high carrier mobility is disclosed. First, prepare two semiconductor wafers. Each wafer has a surface of {100} crystalline orientation and a <110> direction. These wafers are surface-bonded together so that the <110>directions of upper and lower wafers cross each other at a rotation angle, thereby providing a “hybrid” crystal-oriented substrate. On this substrate, form semiconductor regions, one of which is identical in <110> direction to the upper wafer, and the other of which is equal in <110> direction to the lower wafer. In the one region, form a pFinFET having {100} channel plane. In the other region, form an nFinFET having its channel direction in parallel or perpendicular to that of the pFinFET. A CMOS FinFET structure is thus obtained.Type: ApplicationFiled: March 6, 2008Publication date: September 18, 2008Inventors: Yukio Nakabayashi, Junji Koga, Atsuhiro Kinoshita
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Publication number: 20080150040Abstract: An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.Type: ApplicationFiled: February 21, 2008Publication date: June 26, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yukio Nakabayashi, Kazumi Nishinohara, Atsuhiro Kinoshita, Junji Koga
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Patent number: 7358550Abstract: An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.Type: GrantFiled: March 16, 2005Date of Patent: April 15, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Yukio Nakabayashi, Kazumi Nishinohara, Atsuhiro Kinoshita, Junji Koga
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Publication number: 20060220131Abstract: It is possible to reliably implant an impurity into an impurity forming region, and to form a self-aligned silicides on the entire portion of the source and drain regions.Type: ApplicationFiled: March 21, 2006Publication date: October 5, 2006Inventors: Atsuhiro Kinoshita, Junji Koga, Yukio Nakabayashi
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Publication number: 20060199310Abstract: A semiconductor integrated circuit includes a substrate having a main surface to which a first stress is applied; a first channel conductive field effect transistor placed in a first region of the main surface of the substrate, the carrier mobility of a channel of the first channel conductive field effect transistor being improved by the first stress; and a second channel conductive field effect transistor placed in a second region of the main surface of the substrate, and receiving a second stress at a channel thereof, the second stress being opposite to the first stress, the carrier mobility of the channel of the second channel conductive field effect transistor being improved by the second stress, and the second region being independent from the first region.Type: ApplicationFiled: March 3, 2006Publication date: September 7, 2006Inventors: Yukio Nakabayashi, Junji Koga
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Publication number: 20050212055Abstract: An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.Type: ApplicationFiled: March 16, 2005Publication date: September 29, 2005Inventors: Yukio Nakabayashi, Kazumi Nishinohara, Atsuhiro Kinoshita, Junji Koga
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Patent number: 6835600Abstract: A lead frame includes: an outer frame section; a plurality of chip mounting sections which are supported by the outer frame section and on which a plurality of semiconductor chips are mounted; lead sections surrounding the chip mounting sections; connecting sections for connecting and supporting the lead sections and the outer frame section with each other; and an encapsulation region in which the chip mounting sections are encapsulated together in an encapsulation resin. An opening is provided in a plurality of regions of the outer frame section that are each located outside the encapsulation region and along the extension of one of the connecting sections.Type: GrantFiled: May 16, 2003Date of Patent: December 28, 2004Assignee: Matsushita Electric Industrial Co., LTDInventors: Masaki Utsumi, Masashi Funakoshi, Tsuyoshi Hamatani, Takeshi Morikawa, Yukio Nakabayashi
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Publication number: 20030203541Abstract: A lead frame includes: an outer frame section; a plurality of chip mounting sections which are supported by the outer frame section and on which a plurality of semiconductor chips are mounted; lead sections surrounding the chip mounting sections; connecting sections for connecting and supporting the lead sections and the outer frame section with each other; and an encapsulation region in which the chip mounting sections are encapsulated together in an encapsulation resin. An opening is provided in a plurality of regions of the outer frame section that are each located outside the encapsulation region and along the extension of one of the connecting sections.Type: ApplicationFiled: May 16, 2003Publication date: October 30, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Masaki Utsumi, Masashi Funakoshi, Tsuyoshi Hamatani, Takeshi Morikawa, Yukio Nakabayashi
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Patent number: 6603194Abstract: A lead frame includes: an outer frame section; a plurality of chip mounting sections which are supported by the outer frame section and on which a plurality of semiconductor chips are mounted; lead sections surrounding the chip mounting sections; connecting sections for connecting and supporting the lead sections and the outer frame section with each other; and an encapsulation region in which the chip mounting sections are encapsulated together in an encapsulation resin. An opening is provided in a plurality of regions of the outer frame section that are each located outside the encapsulation region and along the extension of one of the connecting sections.Type: GrantFiled: June 13, 2001Date of Patent: August 5, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masaki Utsumi, Masashi Funakoshi, Tsuyoshi Hamatani, Takeshi Morikawa, Yukio Nakabayashi
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Publication number: 20020109973Abstract: A lead frame includes: an outer frame section; a plurality of chip mounting sections which are supported by the outer frame section and on which a plurality of semiconductor chips are mounted; lead sections surrounding the chip mounting sections; connecting sections for connecting and supporting the lead sections and the outer frame section with each other; and an encapsulation region in which the chip mounting sections are encapsulated together in an encapsulation resin. An opening is provided in a plurality of regions of the outer frame section that are each located outside the encapsulation region and along the extension of one of the connecting sections.Type: ApplicationFiled: June 13, 2001Publication date: August 15, 2002Inventors: Masaki Utsumi, Masashi Funakoshi, Tsuyoshi Hamatani, Takeshi Morikawa, Yukio Nakabayashi