Abstract: An n-type impurity layer is formed on a boundary portion between a source/drain and a field oxide film in a portion deeper than the source/drain. Even if a metal silicide layer such as a Co silicide layer extends into a portion under the field oxide film or an end portion of the field oxide film is eroded, therefore, the metal silicide layer is not directly connected to a well, a channel cut injection layer or a channel injection layer and the distance between a pn junction formed by the source/drain and the well and an end portion of the metal silicide layer is not reduced, whereby reliability of an element operation is improved such that a leakage current is suppressed while maintaining the depth of the source/drain.

Abstract: There are provide a semiconductor device capable of increasing the operating speed of MOS transistors and improving current driving capability, and a method of manufacturing such a semiconductor device. A semiconductor device comprises a silicon substrate (1), an element isolation insulation film (2), a gate structure selectively formed on the main surface of the silicon substrate (1), and a sidewall (6) formed on the side face of the gate structure. The gate structure has a laminated structure with a gate insulation film (3) formed of a silicon oxide film, a gate electrode (4) formed of polysilicon, and a cobalt silicide layer (5) stacked in this order.

Abstract: CMOS transistors which can satisfy demand for size reduction and demand for reliability and a manufacturing method thereof are provided. A buried-channel type PMOS transistor is provided only in a CMOS transistor (100B) designed for high voltage; surface-channel type NMOS transistors are formed in a low-voltage NMOS region (LNR) and a high-voltage NMOS region (HNR), and a surface-channel type PMOS transistor is formed in a low-voltage PMOS region (LPR).

Abstract: A MOSFET includes a silicon substrate (1) with trenches (2) formed therein. Each of the trenches (2) is completely filled with a silicon oxy-nitride (9) formed on inner wall faces (2W) and a bottom face (2B) thereof. The ratio between compositions of the silicon oxy-nitride (9) is controlled so that the silicon oxy-nitride (9) is approximately equal in thermal expansion coefficient to silicon. An end portion of the silicon oxy-nitride (9) along an opening of each trench (2) is located at a higher level than a main surface (1S) of the silicon substrate (1), and a surface of the silicon oxy-nitride (9) increases in height from the end portion toward the center thereof. The silicon oxy-nitride (9) has no depressions adjacent to the end portion thereof. Sidewall oxide films (41) and a gate electrode (5) are formed on a gate insulation film (4) formed in an active region.

Abstract: Trench isolation regions of different depths are formed through a simple manufacturing process, and reliability of a semiconductor device is increased. Trenches (103a, 103b) of different widths are formed on a semiconductor substrate (101) on which an underlying film (104) such as a silicon oxide film and a mask material (105) such as a silicon nitride film are formed. Then, an insulating film such as a silicon oxide film is deposited over the entire surface to such a degree that the narrower trench (103a) is filled up. At this time, the wider trench (103b) has an unfilled space in its central portion. a The surface of the substrate (101) is then vertically etched back until it is exposed in the trench 103b. With insulating films (106a, 106b) in the trenches (103a, 103b) as a mask, the surface of the substrate (101) is anisotropically etched vertically to form a deeper bottom (103c) in the trench (103b).

Abstract: Arsenic is ion-implanted through a thin insulative through film formed on an active region in the vicinity of a gate insulating film towards the inside of a semiconductor substrate at a dose of 3E13 cm−2 at an energy of 100 keV at a tilt angle, which is made by an ion implantation direction and a normal direction (NL), of 45 degrees with respect to a (100) surface of the semiconductor substrate, with which a channeling phenomenon can be caused. Next, phosphorus is ion-implanted towards the inside of the semiconductor substrate at a dose of 1E13 cm−2 at an energy of 50 keV at an angle with which no channeling phenomenon can be caused. After that, a sidewall is formed and then arsenic is ion-implanted towards the inside of the semiconductor substrate at a dose of 4E15 cm−2 at an energy of 50 keV at an angle with which no channeling phenomenon can be caused, to form n+ layers.

Abstract: There are provide a semiconductor device capable of increasing the operating speed of MOS transistors and improving current driving capability, and a method of manufacturing such a semiconductor device. A semiconductor device comprises a silicon substrate (1), an element isolation insulation film (2), a gate structure selectively formed on the main surface of the silicon substrate (1), and a sidewall (6) formed on the side face of the gate structure. The gate structure has a laminated structure with a gate insulation film (3) formed of a silicon oxide film, a gate electrode (4) formed of polysilicon, and a cobalt silicide layer (5) stacked in this order.

Abstract: In a method of manufacturing a semiconductor device capable of reducing gate resistance by increasing the width of a conductive layer formed on a gate electrode without increasing the gate length, an extension is formed in an upper surface of a silicon substrate, and thereafter a silicon oxide film and a silicon nitride film are deposited on the overall surface. Then, the silicon nitride film and the silicon oxide film are anisotropically etched in this order. Then, another silicon oxide film is deposited on the overall surface and thereafter anisotropically etched. Then, ion implantation is performed through a gate electrode and a side wall serving as masks, to form an impurity region. Silicon is grown under conditions having selectivity for a silicon oxide film, to form a silicon growth layer. Then, cobalt is deposited on the overall surface and thereafter heat treatment is performed to form a cobalt silicide layer. Thereafter unreacted cobalt is removed.

Abstract: Nitrogen distributed layers 3N and 53N are formed in the vicinity of surfaces of silicon layers 3 and 53 on the silicide layer 11 and 61 sides, respectively. When ions are implanted for forming source/drain regions 9 and 59, a dopant is also implanted into the silicon layers 3 and 53. Consequently, a boron distributed layer 3B or a phosphorus distributed layer 53P is formed in a deeper region than the nitrogen distributed layers 3N and 53N. Cobalt is deposited to cover the silicon layers 3 and 53 and p+-type layers 8 and 58, and silicide layers 11, 61, 10 and 60 are thus formed by a salicide reaction. Interaction of boron and phosphorus (interaction of the dopant in the silicon layer with the silicide layer during a salicide reaction) is suppressed by nitrogen in the nitrogen distributed layers 3N and 53N. As a result, a MOS transistor which comprises gate electrodes 5 and 55 having low resistances and has a predetermined threshold is manufactured.

Abstract: An MIS transistor manufacturing method which can prevent unwanted diffusion of extensions caused by the drive to the source/drain so that the diffusion of the source/drain and the diffusion of the extensions can independently be controlled so as to obtain optimum structure for each. Source/drain are formed by ion implantation using, as a mask, L-shaped silicon nitride films formed on sides of a gate electrode and silicon oxide films covering the silicon nitride films. The silicon oxide films are then removed leaving the silicon nitride films. Impurity ions are then ion-implanted into the main surface of the silicon substrate through the silicon nitride films. Since the silicon nitride films are thicker in the vicinity of the gate electrode and thinner in the vicinity of the source/drain, this process forms extensions penetrating under the gate electrode for a small distance.

Abstract: Trench isolation regions of different depths are formed through a simple manufacturing process, and reliability of a semiconductor device is increased. Trenches (103a, 103b) of different widths are formed on a semiconductor substrate (101) on which an underlying film (104) such as a silicon oxide film and a mask material (105) such as a silicon nitride film are formed. Then, an insulating film such as a silicon oxide film is deposited over the entire surface to such a degree that the narrower trench (103a) is filled up. At this time, the wider trench (103b) has an unfilled space in its central portion. The surface of the substrate (101) is then vertically etched back until it is exposed in the trench 103b. With insulating films (106a, 106b) in the trenches (103a, 103b) as a mask, the surface of the substrate (101) is anisotropically etched vertically to form a deeper bottom (103c) in the trench (103b).

Abstract: In a buttonhole sewing machine, a sewing mechanism and a feed bracket are controlled to form a buttonhole defined by settings, such as zigzag stitch length, zigzag pitch, bar-tack length, bar-tack pitch, and cutter space. The buttonhole can be set on the operation panel and changed to various shapes by changing the above settings. In particular, the left and right zigzag stitch widths can be set differently, and the front and rear bar-tack lengths can be also set differently. Thus, the balance of the buttonhole can be finely adjusted.

Abstract: The invention relates to a sewing machine provided with a needle reciprocated according to rotations of a main shaft and work feeding devices actuated synchronously with rotations of the main shaft, setting a margin to sew from a trailing edge to a sewing end position. The sewing machine includes devices for computing a terminal stitch length according to a set margin width. Control devices are provided for controlling a sewing to be carried out for coping with that which corresponds to the terminal stitch length computed by the computing device. The sewing machine further comprises computing devices for applying a correction to at least one of a number of stitches and a feed pitch, as occasion demands, where there arises the remainder as the result of an operation of the computing devices, and control devices for controlling the sewing to be carried out according to the computed result.

Abstract: A sewing machine forms a seam in the form of a series of stitches for a length preset by the operator. The length of the seam formed is computed from feed pitches data each generated when one stitch is formed. The operation of the sewing machine is stopped when the computed seam length coincides with the preset seam length.