Patents by Inventor Yu-Min Wang

Yu-Min Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250087601
    Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Inventors: Chao-Chiang PU, Chi-Ching HO, Yi-Min FU, Yu-Po WANG, Po-Yuan SU
  • Publication number: 20250088778
    Abstract: A redundant system and a redundancy method of a fronthaul network are provided. The redundant system includes a first fronthaul multiplexer. The first fronthaul multiplexer includes a first group port, a second group port, a first cascade port, a first protect port, a first active port, and a first uplink circuit. The first uplink circuit includes a first summation circuit and a second summation circuit. A plurality of input terminals of the first summation circuit are coupled to the first group port and the second group port respectively, and an output terminal of the first summation circuit is coupled to the first protect port. A plurality of input terminals of the second summation circuit are coupled to the first cascade port and the output terminal of the first summation circuit respectively, and an output terminal of the second summation circuit is coupled to the first active port.
    Type: Application
    Filed: October 3, 2023
    Publication date: March 13, 2025
    Applicant: Ufi Space co., Ltd.
    Inventors: Yu-Min Wang, Meng-Chiao Lin, Yu Chih Wang, Che-Hung Liu
  • Publication number: 20250087625
    Abstract: A zone heater assembly of a reflow solder tool includes a gas deflector having a single-layer structure. The single-layer structure may include one or more gas-permeating patterns through which a process gas is to flow from one or more gas outlets to a gas exhaust of the zone heater assembly. The one or more gas-permeating patterns in the single-layer structure promote uniformity of gas flow through the gas exhaust and into a heating zone of the reflow solder tool. The uniformity of the gas flow of the process gas enables convection heat provided by the process gas to be uniformly distributed across the heating zone. In this way, the gas deflector described herein may decrease hot spots and/or cold spots in the heating zone, which enables greater flexibility in placement of semiconductor package substrates on a conveyor device of the reflow solder tool.
    Type: Application
    Filed: January 11, 2024
    Publication date: March 13, 2025
    Inventors: Yu-Young WANG, Chun-Min LIN, Min-Yu WU, Chih-Jen WU
  • Patent number: 12224263
    Abstract: A method for transferring an electronic device includes steps as follows. A flexible carrier having a first surface on which the electronic device to be transferred is disposed and a second surface, a target substrate, a target substrate, and a light-transmissible pin having a pressing end are provided. The flexible carrier is spaced from the target substrate with the first surface thereof facing the target substrate. The flexible carrier is deformed by exerting the pin to press the second surface with the pressing end thereof at a position corresponding to the electronic device until the electronic device is in contact with the target substrate. An energy beam emitted from a light source standing outside the pin and then traveling through the pin and going out from the pressing end to bond the electronic device onto the target substrate is applied. The pin is released from pressing the flexible carrier.
    Type: Grant
    Filed: March 5, 2024
    Date of Patent: February 11, 2025
    Assignee: Micraft System Plus Co., Ltd.
    Inventors: Yu-Min Huang, Sheng Che Huang, Chingju Lin, Wei-Hao Wang
  • Patent number: 12224739
    Abstract: A fast-transient buffer is shown. The fast-transient buffer has a flipped voltage follower coupled between the input terminal and the output terminal of the fast-transient buffer, and a first MOS transistor coupled to the flipped voltage follower as well as the output terminal of the fast-transient buffer. The first MOS transistor regulates the output voltage of the output terminal of the fast-transient buffer, in the opposite direction in comparison with an output voltage regulation direction due to the flipped voltage follower.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: February 11, 2025
    Assignee: MEDIATEK INC.
    Inventors: Yueh-Min Chen, Ting-Yang Wang, Yu-Hsin Lin, Wen-Chieh Wang
  • Publication number: 20250048648
    Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a magnetic tunneling junction (MTJ) on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes metal and the blocking layer includes a grid line pattern according to a top view.
    Type: Application
    Filed: October 16, 2024
    Publication date: February 6, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jia-Rong Wu, I-Fan Chang, Rai-Min Huang, Ya-Huei Tsai, Yu-Ping Wang
  • Publication number: 20250038113
    Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.
    Type: Application
    Filed: October 16, 2024
    Publication date: January 30, 2025
    Inventors: Chao-Chiang PU, Chi-Ching HO, Yi-Min FU, Yu-Po WANG, Shuai-Lin LIU
  • Publication number: 20250040149
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.
    Type: Application
    Filed: October 16, 2024
    Publication date: January 30, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Huei Tsai, Rai-Min Huang, Yu-Ping Wang, Hung-Yueh Chen
  • Patent number: 12211937
    Abstract: A semiconductor device and method of manufacture are provided which help to support contacts while material is removed to form air gaps. In embodiments a contact is formed with an enlarged base to help support overlying portions of the contact. In other embodiments a scaffold material may also be placed prior to the formation of the air gaps in order to provide additional support.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ching-Feng Fu, Guan-Ren Wang, Yun-Min Chang, Yu-Lien Huang
  • Publication number: 20250015816
    Abstract: A multiplexer and a method for combining radio frequency (RF) data are provided. The method is described below. The first output management circuit receives first data and second data and determines whether a first power of the first data and a second power of the second data match a default rule. The first output management circuit output first output data including the second data to a combine circuit coupled to the first output management circuit in response to the first power and the second power not matching the default rule. The combine circuit receives multiple output data from the output management circuits respectively and combines the output data to output combined RF data. The output management circuits include the first output management circuit. The output data includes the first output data.
    Type: Application
    Filed: July 26, 2023
    Publication date: January 9, 2025
    Applicant: Ufi Space co., Ltd.
    Inventors: Yu-Min Wang, Meng-Chiao Lin
  • Publication number: 20250008823
    Abstract: Sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display, such as an organic light-emitting diode (OLED) display, are provided. In one example, a sub-pixel includes a substrate, adjacent overhang structures, an anode, an OLED material, a cathode, an encapsulation layer stack. The encapsulation layer stack includes a first layer, a second layer disposed over the first layer, and a third layer. The first layer and the second layer have a first portion disposed over the cathode, a second portion disposed over a sidewall of each overhang structure, and a third portion disposed under an underside surface of an extension of each overhang structure. A gap is defined by contact of the first portion of the second layer and the third portion of the second layer. The third layer is disposed over the second layer outside of the gap.
    Type: Application
    Filed: March 4, 2024
    Publication date: January 2, 2025
    Inventors: Zongkai WU, Pei Chia CHEN, Wen-Hao WU, Jungmin LEE, Chung-chia CHEN, Yu-Hsin LIN, Kevin CHEN, Wenhui LI, Yu-Min WANG, Lai ZHAO, Soo Young CHOI
  • Publication number: 20240430834
    Abstract: A delay compensation method and device are provided. The method includes: obtaining a control plane message; obtaining a path delay of each of multiple radio units, and determining a compensation time length corresponding to each of the radio units based on a reference path delay and the path delay of each of the radio units; and sending the control plane message to each of the radio units based on the compensation time length corresponding to each of the radio units.
    Type: Application
    Filed: July 6, 2023
    Publication date: December 26, 2024
    Applicant: Ufi Space co., Ltd.
    Inventors: Yu-Min Wang, Meng-Chiao Lin
  • Publication number: 20240352584
    Abstract: The present disclosure generally provides an apparatus and method for gas diffuser support structure for a vacuum chamber. The gas diffuser support structure comprises a backing plate having a central bore, and a gas deflector having a length and a width unequal to the length coupled to the backing plate by a plurality of outward fasteners coupled to a plurality of outward threaded holes formed in the backing plate, in which a spacer is disposed between the backing plate and the gas deflector, and in which a length to width ratio of the gas deflector is about 0.1:1 to about 10:1.
    Type: Application
    Filed: March 27, 2024
    Publication date: October 24, 2024
    Inventors: Yu-Hsuan WU, Teng Mao WANG, Yan-Chi PAN, Yi-Jiun SHIU, Jrjyan Jerry CHEN, Cheng-yuan LIN, Hsiao-Ling YANG, Yu-Min WANG, Wen-Hao WU
  • Patent number: 12127147
    Abstract: A synchronization correction method, a master device, and a slave device are provided. The method includes: transmitting a synchronization signal frame to a slave device during a first period of an ith second, where the synchronization signal frame includes a synchronization header, a first pulse per second (1PPS) signal, first time of date information, and first phase compensation information, where the first phase compensation information is configured to request the slave device to correct a transmission time point at which a first reference 1PPS signal is transmitted during a second period of the ith second; receiving the first reference 1PPS signal from the slave device during the second period of the ith second; and determining second phase compensation information transmitted to the slave device according to a receiving time point at which the first reference 1PPS signal is received during a first period of an (i+1)th second.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: October 22, 2024
    Assignee: Ufi Space co., Ltd.
    Inventors: Yu-Min Wang, Chih Wei Chang
  • Publication number: 20240259151
    Abstract: A distributed synchronization system including a management device and a plurality of synchronization devices is provided. The management device includes a network input interface and a network output interface, and is configured to: decode a precision time protocol packet to obtain a reference 1 pulse per second signal, a reference frequency signal, and reference time of day information; send a reference synchronization signal and a reference control signal to a first synchronization device through the network output interface. The reference synchronization signal includes the reference 1 pulse per second signal, the reference frequency signal and the reference time of day information. The reference control signal requests the first synchronization device to synchronize with the management device.
    Type: Application
    Filed: January 31, 2023
    Publication date: August 1, 2024
    Applicant: Ufi Space co., Ltd.
    Inventors: Chih-Chin Chang, Yu-Min Wang, Hai-Jian Zhang, Kai-Yu Yang
  • Patent number: 11956134
    Abstract: The disclosure provides a multi-link receiving method and a multi-link receiver. The method includes the following. A reference delay range of a j-th data section is determined according to a preset delay time and a receiving time point of the j-th data section of an i-th data frame. In response to determining that the j-th data section is first received among an N number of data sections of the i-th data frame, the reference delay range of the j-th data section is taken as a designated delay range. In response to determining that receiving time points of the data sections of the i-th data frame are each within the designated delay range, the i-th data frame is restored based on the N number of data sections of the i-th data frame.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: April 9, 2024
    Assignee: Ufi Space co., Ltd.
    Inventor: Yu-Min Wang
  • Patent number: 11889057
    Abstract: A method for a video encoder includes steps of: receiving a series of input frames; performing at least one of intra-prediction and inter-prediction on the series of input frames for generating at least one of an intra frame (I-frame), a predictive frame (P-frame), and a key predictive frame (key P-frame); generating an encoded bitstream with respect to a first input frame determined as the I-frame among the series of input frames; and performing inter-prediction on a second input frame determined as a key P-frame among the series of input frames according to a first reference frame which is derived from the encoded bitstream with respect to the first input frame.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: January 30, 2024
    Assignee: NOVATEK Microelectronics Corp.
    Inventor: Yu-Min Wang
  • Publication number: 20230265562
    Abstract: Exemplary methods of forming a silicon-oxygen-and-nitrogen-containing barrier layer are described. The methods include flowing deposition gases into a substrate processing region of a processing chamber, where the deposition gases include a silicon-containing gas and a nitrogen-containing gas. A deposition plasma is generated from the deposition gases in the substrate processing region. A silicon-oxygen-and-nitrogen-containing layer is deposited on a substrate from the deposition plasma, where the silicon-oxygen-and-nitrogen-containing layer is characterized by thickness of less than or about 2000 ?. The methods further include exposing a surface of the silicon-oxygen-and-nitrogen-containing layer to a treatment plasma to form a treated silicon-oxygen-and-nitrogen-containing layer, where the treatment plasma is formed from a nitrogen-containing gas and is silicon free.
    Type: Application
    Filed: February 22, 2022
    Publication date: August 24, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Fei Wu, Tae Kyung Won, Yu-Min Wang, Young Dong Lee
  • Patent number: 11609701
    Abstract: The disclosure provides a power management method and a power management device. The method includes: reading a specific memory which includes a plurality of error data records; selecting a specific data record based on a usage status indicator of each error data record; sequentially sending an enable signal to each hardware device; in response to determining that an enable successful response corresponding to the enable signal is not received from a specific hardware device, or a boot alarm is received, at least obtaining a low pin count value and a power management status; recording the low pin count value and the power management status in the specific data record, and accordingly updating the usage status indicator of the specific data record.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: March 21, 2023
    Assignee: Ufi Space co., Ltd.
    Inventors: Yu-Min Wang, Chih-Tsao Chang, Ying-Hsiu Lai
  • Patent number: 11575405
    Abstract: The disclosure provides a method for correcting a 1 pulse per second (1PPS) signal and a timing receiver. In the embodiments of the disclosure, the proposed method allows the timing receiver to provide a corrected 1PPS signal with better quality to back-end slave devices, thereby ensuring that the synchronization effect of the slave devices is not overly affected by jitter in a single 1PPS signal.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: February 7, 2023
    Assignee: Ufi Space co., Ltd.
    Inventors: Yu-Min Wang, Yu Chih Wang