Abstract: A transmission device includes a daisy chain structure composed of at least three daisy chain units arranged periodically and continuously. Each of the daisy chain units includes first, second and third conductive lines, and first and second conductive pillars. The first and second conductive lines at a first layer extend along a first direction and are discontinuously arranged. The third conductive line at a second layer extends along the first direction and is substantially parallel to the first and second conductive lines. The first conductive pillar extends in a second direction. The second direction is different from the first direction. A first part of the first conductive pillar is connected to the first and third conductive lines. The second conductive pillar extends in the second direction. A first part of the second conductive pillar is connected to the second and third conductive lines.

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first electrode, a second electrode on one side of the first electrode, and a resistive switching film between the first electrode and the second electrode. The first electrode, the resistive switching film and the second electrode are arranged along the first direction. The second semiconductor structure includes a first via and a first metal layer on the first via along a second direction and electrically connected to the first via. The first direction is perpendicular to the second direction. An upper surface of the first electrode, an upper surface of the second electrode, an upper surface of the resistive switching film and an upper surface of the first metal layer are coplanar.

Abstract: The disclosure provides a multi-link receiving method and a multi-link receiver. The method includes the following. A reference delay range of a j-th data section is determined according to a preset delay time and a receiving time point of the j-th data section of an i-th data frame. In response to determining that the j-th data section is first received among an N number of data sections of the i-th data frame, the reference delay range of the j-th data section is taken as a designated delay range. In response to determining that receiving time points of the data sections of the i-th data frame are each within the designated delay range, the i-th data frame is restored based on the N number of data sections of the i-th data frame.

Abstract: A heterogeneous integration semiconductor package structure including a heat dissipation assembly, multiple chips, a package assembly, multiple connectors and a circuit substrate is provided. The heat dissipation assembly has a connection surface and includes a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface. The chips are disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer. The package assembly surrounds the chips and includes a second redistribution structure layer disposed on a lower surface and multiple conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer. The connectors are disposed on the package assembly and electrically connected to the second redistribution structure layer.

Abstract: A semiconductor structure includes a composite redistribution structure, a first interconnect device and an integrated circuit (IC) package component. The composite redistribution structure includes a first redistribution structure, a second redistribution structure and a third redistribution structure. The second redistribution structure is located between the first redistribution structure and the third redistribution structure. The first interconnect device is embedded in the second redistribution structure. The first interconnect device includes a plurality of metal connectors leveled with a surface of the second redistribution structure and electrically connected to the third redistribution structure. The IC package component is disposed over the third redistribution structure and electrically connected to the first interconnect device via the third redistribution structure.

Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Abstract: An example electronic device includes a controller to determine a user touch detection by a power adaptor coupled to the electronic device to operate the electronic device in an AC power mode. The power adaptor may comprise a proximity sensor to detect a user touch for detachment of the power adaptor from the electronic device, and a control circuit to operate a configuration pin in a low output mode to signal user touch detection. The controller may initiate central processing unit (CPU) throttling to reduce power consumption by the electronic device. The controller may further stop CPU throttling in response to detecting that the power adaptor has been detached from the electronic device. Further, the controller may switch the electronic device to a DC power mode to operate using DC power supplied by a battery of the electronic device in response to power adaptor detachment.

Abstract: A method for a video encoder includes steps of: receiving a series of input frames; performing at least one of intra-prediction and inter-prediction on the series of input frames for generating at least one of an intra frame (I-frame), a predictive frame (P-frame), and a key predictive frame (key P-frame); generating an encoded bitstream with respect to a first input frame determined as the I-frame among the series of input frames; and performing inter-prediction on a second input frame determined as a key P-frame among the series of input frames according to a first reference frame which is derived from the encoded bitstream with respect to the first input frame.

Abstract: Exemplary methods of forming a silicon-oxygen-and-nitrogen-containing barrier layer are described. The methods include flowing deposition gases into a substrate processing region of a processing chamber, where the deposition gases include a silicon-containing gas and a nitrogen-containing gas. A deposition plasma is generated from the deposition gases in the substrate processing region. A silicon-oxygen-and-nitrogen-containing layer is deposited on a substrate from the deposition plasma, where the silicon-oxygen-and-nitrogen-containing layer is characterized by thickness of less than or about 2000 ?. The methods further include exposing a surface of the silicon-oxygen-and-nitrogen-containing layer to a treatment plasma to form a treated silicon-oxygen-and-nitrogen-containing layer, where the treatment plasma is formed from a nitrogen-containing gas and is silicon free.

Abstract: The disclosure provides a power management method and a power management device. The method includes: reading a specific memory which includes a plurality of error data records; selecting a specific data record based on a usage status indicator of each error data record; sequentially sending an enable signal to each hardware device; in response to determining that an enable successful response corresponding to the enable signal is not received from a specific hardware device, or a boot alarm is received, at least obtaining a low pin count value and a power management status; recording the low pin count value and the power management status in the specific data record, and accordingly updating the usage status indicator of the specific data record.

Abstract: The disclosure provides a method for correcting a 1 pulse per second (1PPS) signal and a timing receiver. In the embodiments of the disclosure, the proposed method allows the timing receiver to provide a corrected 1PPS signal with better quality to back-end slave devices, thereby ensuring that the synchronization effect of the slave devices is not overly affected by jitter in a single 1PPS signal.

Abstract: A method for manufacturing a bending-tolerant multilayered flexible circuit board (FPC) suitable for use in a disposable biosensor chip includes manufacturing and bending a single-sided FPC. The single-sided FPC includes a base layer, a wiring layer, and through holes. The wiring layer includes first and second wiring areas. A first bending area is formed between each first wiring area and the corresponding second wiring area, the through holes forming an easy bending line. The second wiring area is bent relative to the first wiring area along the bending line to obtain the multilayered FPC.

Abstract: A method for manufacturing a flex-tolerant three-dimensional printed antenna suitable for use in an electronic device provides a three-dimensional printed antenna with base layer, radiation layer, through holes, and feeder. The radiation layer includes a first radiation region, at least one second radiation region, and a feed end. A region between the first and second radiation regions is defined as a bent region. The radiation layer is formed by a screen-printing plate by a planar printing process. The through holes on the bent region form a line for bending. The feeder is electrically connected to the feed end. The second radiation region is canted from the bending line with respect to the first radiation region to form the three-dimensional printed antenna. The three-dimensional printed antenna and an electronic device are also disclosed.

Abstract: Methods and image processing devices for encoding and decoding private data are proposed. The method for encoding private data includes to receive an original video frame, mask at least one private area in the original video frame to generate a protected video frame, generate a first encoded frame by encoding the protected video frame, and generate at least one output bitstream for streaming or storage according to the first encoded frame. The method for decoding private data includes to receive at least one input video bitstream to obtain a first encoded bitstream and a second encoded bitstream, decode the first encoded bitstream to generate a protected video frame including image data associated with at least one private area, and output the protected video frame to a display queue such that the at least one private area is displayed.

Abstract: A synchronization device and a synchronization method for synchronizing a first node and a second node are provided. The first node supports a first time protocol profile, and the second node supports a second time protocol profile. The synchronization method includes: providing a system operating time by a counter; communicating with the first node based on the first time protocol profile to obtain first synchronization information; calculating a time delay according to the first synchronization information, and correcting the system operating time according to the time delay to generate a corrected system operating time; and communicating with the second node based on the second time protocol profile so as to provide the second node with second synchronization information according to the corrected system operating time.

Abstract: A byte stuffing circuit and a byte stuffing method are provided. The byte stuffing method includes: receiving a first data stream and generating a second data stream according to the first data stream, where a first size of the first data stream is N bytes, and a second size of the second data stream is 2N bytes; in response to an Xth byte of the second data stream matching a first flag byte, overwriting the Xth byte with a first stuffing byte, and inserting a second stuffing byte into an (X+1)th byte of the second data stream, where X is a positive integer between 1 and 2N?1; combining a remnant data stream and a first part of the second data stream to generate a third data stream, and configuring a second part of the second data stream as the remnant data stream; and outputting the third data stream.

Abstract: A method for a video encoder includes steps of: receiving a series of input frames; performing at least one of intra-prediction and inter-prediction on the series of input frames for generating at least one of an intra frame (I-frame), a predictive frame (P-frame), and a key predictive frame (key P-frame); generating an encoded bitstream with respect to a first input frame determined as the I-frame among the series of input frames; and performing inter-prediction on a second input frame determined as a key P-frame among the series of input frames according to a first reference frame which is derived from the encoded bitstream with respect to the first input frame.

Abstract: A synchronization device and a synchronization method for synchronizing a first node and a second node are provided. The first node supports a first time protocol profile, and the second node supports a second time protocol profile. The synchronization method includes: providing a system operating time by a counter; communicating with the first node based on the first time protocol profile to obtain first synchronization information; calculating a time delay according to the first synchronization information, and correcting the system operating time according to the time delay to generate a corrected system operating time; and communicating with the second node based on the second time protocol profile so as to provide the second node with second synchronization information according to the corrected system operating time.