Patents by Inventor Yun Chi

Yun Chi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250056857
    Abstract: An integrated circuit device includes a Janus transition metal dichalcogenide layer, a first gate structure, and a second gate structure. The Janus transition metal dichalcogenide layer has opposite first and second sides. The first gate structure is on the first side of the Janus transition metal dichalcogenide layer. A second gate structure is on the second side of the Janus transition metal dichalcogenide layer.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 13, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Yuh-Renn WU, Yun-Ping CHIU, Hsin-Wen HUANG, Hsiu-Chi PAI
  • Publication number: 20250056835
    Abstract: An integrated circuit structure includes a semiconductor substrate, first and second source/drain features, a gate dielectric layer, a gate electrode, a field plate electrode, first and second metal silicide layers, a dielectric layer, and a spacer. The gate electrode and the field plate electrode are over the gate dielectric layer and respectively vertically overlapping a well region and a drift region in the semiconductor substrate. A first sidewall of the field plate electrode faces the gate electrode. The first and second metal silicide layers are over the gate electrode and the field plate electrode, respectively. The dielectric layer has a first portion between the gate electrode and the first sidewall of the field plate electrode and a second portion below a bottom surface of the field plate electrode. The spacer is alongside a second sidewall of the field plate electrode and over the second portion of the dielectric layer.
    Type: Application
    Filed: October 31, 2024
    Publication date: February 13, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Bo SHU, Yun-Chi WU
  • Publication number: 20250047948
    Abstract: Interaction is created between users and streamers even when the users give gifts to the streamers outside live-streams. Provided is a terminal of a user, which includes: one or more processors; and memory storing one or more computer programs configured to be executed by the one or more processors. The one or more computer programs include instructions for: receiving, from the user, an instruction to use a gift for a streamer while the user is not participating in a live-stream of the streamer; and causing an output unit to output an effect corresponding to the use of the gift by the user while the streamer is live-streaming.
    Type: Application
    Filed: October 21, 2024
    Publication date: February 6, 2025
    Inventors: Yu-Shan YANG, Yung-Chi HSU, Sheng-Kai HSU, Ching-Jan WANG, Yun-An LIN
  • Patent number: 12211869
    Abstract: An image sensor includes an array of image pixels and black level correction (BLC) pixels. Each BLC pixel includes a BLC pixel photodetector, a BLC pixel sensing circuit, and a BLC pixel optics assembly configured to block light that impinges onto the BLC pixel photodetector. Each BLC pixel optics assembly may include a first portion of a layer stack including a vertically alternating sequence of first material layers having a first refractive index and second material layers having a second refractive index. Additionally or alternatively, each BLC pixel optics assembly may include a first portion of a layer stack including at least two metal layers, each having a respective wavelength sub-range having a greater reflectivity than another metal layer. Alternatively or additionally, each BLC pixel optics assembly may include an infrared blocking material layer that provides a higher absorption coefficient than color filter materials within image pixel optics assemblies.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Feng-Chien Hsieh, Yun-Wei Cheng, Kuo-Cheng Lee, Hsin-Chi Chen
  • Patent number: 12209662
    Abstract: A seal, a fluid assembly comprising same, and a fluid device. The seal comprises a body portion; first through holes are formed in the seal; the seal further has first sealing portions corresponding to the first through holes; there are at least two first through holes; each first sealing portion comprises a first extension portion and a second extension portion; the first extension portion and the second extension portion are located on opposite sides of the body portion; the first extension portion and the second extension portion extend from the body portion toward the first through holes; the distance between the first extension portion and the second extension portion is greater than the height of the body portion; and the first extension portion is a closed raised structure, and the second extension portion is also a closed raised structure.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: January 28, 2025
    Assignee: ZHEJIANG SANHUA AUTOMOTIVE COMPONENTS CO., LTD.
    Inventors: Lixin Wang, Yun Wang, Long Lin, Cancan Shen, Jianhua Chi
  • Patent number: 12209680
    Abstract: A drive device includes a housing, a motor and a transmission assembly; the housing includes a first casing and a second casing; the first casing includes a first protruding portion and a second protruding portion; the second casing includes a third protruding portion; the transmission assembly includes a first-stage worm, a second-stage worm and a transmission wheel; the first-stage worm includes a first tooth-shaped portion; the second-stage worm includes a second tooth-shaped portion; the first protruding portion and the second protruding portion both limitedly cooperate with the second-stage worm; along the axial direction of the second tooth-shaped portion, the first protruding portion is located on one side of the second tooth-shaped portion; the second protruding portion is located on the other side of the second tooth-shaped portion; and the distance between the third protruding portion and the transmission wheel is within a preset range.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: January 28, 2025
    Assignee: ZHEJIANG SANHUA AUTOMOTIVE COMPONENTS CO., LTD.
    Inventors: Lixin Wang, Yun Wang, Long Lin, Jianhua Chi
  • Publication number: 20250010728
    Abstract: A motor driving device includes a battery module and a conversion circuit. The conversion circuit drives a motor in a driving mode and charges the battery module in a charging mode. The conversion circuit includes a determination circuit, a controller, and a first phase upper arm switch circuit. The first phase upper arm switch circuit includes a power switch and a transistor. First terminals, second terminal, and control terminals of both the power switch and the transistor are respectively coupled to a positive power supply terminal of the battery module, a first phase node, and the controller. In the charging mode, when a first phase voltage value located at the first phase node is greater than a battery voltage value located at the positive power supply terminal, the determination circuit notifies the controller to turn on the transistor.
    Type: Application
    Filed: April 15, 2024
    Publication date: January 9, 2025
    Applicant: APh ePower Co., Ltd.
    Inventors: Jyh-Wei Chen, Hsiu-Hsien Su, Yun-Chi Tzeng
  • Patent number: 12166121
    Abstract: An integrated circuit structure includes a semiconductor substrate, a first source/drain feature, a second source/drain feature, a gate dielectric layer, a gate electrode, a field plate electrode, and a dielectric layer. The semiconductor substrate has a well region and a drift region therein. The first source/drain feature is in the well region. The second source/drain feature is in the semiconductor substrate. The drift region is between the well region and the second source/drain feature. The gate dielectric layer is over the well region and the drift region. The gate electrode is over the gate dielectric layer and vertically overlapping the well region. The field plate electrode is over the gate dielectric layer and vertically overlapping the drift region. The dielectric layer is between the gate electrode and the field plate electrode. A top surface of the gate electrode is free of the dielectric layer.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Bo Shu, Yun-Chi Wu
  • Patent number: 12165955
    Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.
    Type: Grant
    Filed: November 22, 2023
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Josh Lin, Chung-Jen Huang, Yun-Chi Wu, Tsung-Yu Yang
  • Publication number: 20240380219
    Abstract: A wireless charging system is provided. The wireless charging system includes a wireless power supply platform, a first device, and a second device. The wireless power supply platform provides a wireless suppling power. The first device includes a first power receiving circuit, a first power switch, and a first control circuit. The second device includes a second power receiving circuit, a second power switch, and a second control circuit. The second control circuit communicates with the first control circuit to determine a coordinated switching state of the first power switch and the second power switch. The coordinated switching state determines a first output voltage value generated by the first power receiving circuit according to the wireless suppling power and a second output voltage value generated by the second power receiving circuit according to the wireless suppling power.
    Type: Application
    Filed: April 15, 2024
    Publication date: November 14, 2024
    Applicant: APh ePower Co., Ltd.
    Inventors: Hsiu-Hsien Su, Tsung-Shiun Lee, Yun-Chi Tzeng
  • Patent number: 12144173
    Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.
    Type: Grant
    Filed: June 2, 2023
    Date of Patent: November 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Bo Shu, Chung-Jen Huang, Yun-Chi Wu
  • Publication number: 20240372011
    Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.
    Type: Application
    Filed: July 12, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Bo SHU, Yun-Chi WU, Chung-Jen HUANG
  • Publication number: 20240347626
    Abstract: An LDMOS transistor device includes a stepped isolation structure over a substrate, a gate electrode disposed over a portion of the stepped isolation structure, a source region disposed in the substrate, and a drain region disposed in the substrate. The stepped isolation structure includes a first portion having a first thickness, and a second portion having a second thickness greater than the first thickness. The second portion includes dopants. The drain region is adjacent to the stepped isolation structure.
    Type: Application
    Filed: April 12, 2023
    Publication date: October 17, 2024
    Inventors: TSUNG-HUA YANG, CHENG-BO SHU, CHIA-TA HSIEH, PING-CHENG LI, PO-WEI LIU, SHIH-JUNG TU, TSUNG-YU YANG, YUN-CHI WU, YU-WEN TSENG
  • Publication number: 20240339533
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a source region and a drain region arranged over and/or within a substrate. Further, a shallow trench isolation (STI) structure is arranged within the substrate and between the source and drain regions. A gate electrode is arranged over the substrate, over the STI structure, and between the source and drain regions. A portion of the gate electrode extends into the STI structure such that a bottommost surface of the portion of the gate electrode is arranged between a topmost surface of the STI structure and a bottommost surface of the STI structure.
    Type: Application
    Filed: June 20, 2024
    Publication date: October 10, 2024
    Inventors: Yuan-Cheng Yang, Yun-Chi Wu, Shih-Jung Tu
  • Patent number: 12114503
    Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: October 8, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
  • Publication number: 20240317071
    Abstract: A driving device and a driving method for driving a motor of an electric auxiliary vehicle are provided. The driving device includes a battery module, a transducer, a control circuit. The battery module stores a driving power. When an acceleration command is received, the control circuit controls the transducer to enter a first mode. In the first mode, the transducer provides the driving power to the motor. When a brake command is received, the control circuit controls the transducer to enter a second mode. In the second mode, the transducer provides an inductive power generated by the motor to the battery module. When the acceleration and brake commands are not received and a user does not apply an acceleration force to the electric auxiliary vehicle, the control circuit controls the transducer to enter a third mode. In the third mode, the transducer provides the inductive power to the battery module.
    Type: Application
    Filed: February 16, 2024
    Publication date: September 26, 2024
    Applicant: APh ePower Co., Ltd.
    Inventors: Hsiu-Hsien Su, Kuan-Chieh Huang, Yun-Chi Tzeng
  • Patent number: 12094984
    Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Cheng-Bo Shu, Yun-Chi Wu, Chung-Jen Huang
  • Publication number: 20240293948
    Abstract: A holding device applied to a cutting apparatus to hold an object to be cut includes a holding element and a plurality of damping particles. The holding element is used for holding the object to be cut, and the holding element includes at least one accommodating cavity. Each accommodating cavity extends inward from the outer surface of the holding element to form an accommodating space. The plurality of damping particles is placed in at least one accommodating cavity. During the cutting process of the object to be cut, the plurality of damping particles generates collision and friction with each other or with the cavity wall of the accommodating cavity to reduce the vibration generated by the object to be cut, thereby reducing the surface warpage of a plurality of small-volume objects formed after cutting the object to be cut.
    Type: Application
    Filed: May 31, 2023
    Publication date: September 5, 2024
    Inventor: YUN-CHI CHUNG
  • Patent number: 12062038
    Abstract: Technology is disclosed for transferring money anonymously between a sender and a recipient by use of a one-time use token. The method includes generating a one-time use token account for association with a one-time use token. The method includes generating the token and providing the token to the sender device in a machine-readable and transferable format. The method includes receiving a request to charge the one-time use token account after the token has been provided to the recipient device as a form of payment for a transaction. The method includes determining that an amount of the transaction is less than an amount of funds associated with the token and that the time of the transaction is within a time period for the use of the token. The method includes facilitating a transfer to the recipient account and deducting the amount of the transaction from a sender account.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: August 13, 2024
    Assignee: Block, Inc.
    Inventors: Nathan P. McCauley, Yun Chi, Rong Yan
  • Publication number: 20240258374
    Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.
    Type: Application
    Filed: February 5, 2024
    Publication date: August 1, 2024
    Inventors: Yun-Chi WU, Tsung-Yu YANG, Cheng-Bo SHU, Chien Hung LIU