Abstract: Embodiments of the present disclosure relate to a solution for translation verification and correction. According to the solution, a neural network is trained to determine an association degree among a group of words in a source or target language. The neural network can be used for translation verification and correction. According to the solution, a group of words in a source language and translations of the group of words in a target language are obtained. An association degree among the group of words and an association degree among the translations can be determined by using the trained neural network. Then, whether there is a wrong translation can be determined based on the association degrees. In some embodiments, corresponding methods, systems and computer program products are provided.

Abstract: According to an aspect, a computer-implemented method includes accessing a profile of a user that indicates a likelihood that the user will execute each of a plurality of types of processing when training a new AI model. A runtime matrix that includes identifiers of runtime environments is accessed. The matrix also includes, for each of the runtime environments, a frequency of use of the runtime environment to train previously trained AI models using each of the plurality of types of processing. One or more of the runtime environments is selected for output to the user based at least in part on the profile of the user and the runtime matrix. Identifiers of the selected one or more of the runtime environments are output to a user interface of the user along with a suggestion to use one of the selected one or more of the runtime environments.

Abstract: An image sensor device has a first number of first pixels disposed in a substrate and a second number of second pixels disposed in the substrate. The first number is substantially equal to the second number. A light-blocking structure disposed over the first pixels and the second pixels. The light-blocking structure defines a plurality of first openings and second openings through which light can pass. The first openings are disposed over the first pixels. The second openings are disposed over the second pixels. The second openings are smaller than the first openings. A microcontroller is configured to turn on different ones of the second pixels at different points in time.

Abstract: A data collecting system including a component assembled in an electric vehicle, a data collector connected to the component through a bus of the electric vehicle, and a debug server connected to the data collector is disclosed. The component collects different data from the electric vehicle and performs different sending procedures respectively under different situations including: a regular sending-procedure sends regular data to the bus based on a regular frequency; a high-speed sending-procedure starts collecting high-speed data and sending the same to the bus based on a high-speed frequency after a condition is satisfied; and a high-resolution sending-procedure sends high-resolution data to the bus after an error occurs, wherein the high-resolution data is collected within a period of time before and after the error occurs. The data collector collects these data from the bus. The debug server analyzes the data collected by the data collector.

Abstract: A semiconductor structure includes a substrate with a first surface and a second surface opposite to the first surface, a first and a second shallow trench isolations disposed in the substrate and on the second surface, a deep trench isolation structure in the substrate and coupled to the first shallow trench isolation, a first dielectric layer disposed on the first surface and coupled to the deep trench isolation structure, a second dielectric layer disposed over the first dielectric layer and coupled to the deep trench isolation structure, a third dielectric layer comprising a horizontal portion disposed over the second dielectric layer and a vertical portion coupled to the horizontal portion, and a through substrate via structure penetrating the substrate from the first surface to the second surface and penetrating the second shallow trench isolation.

Abstract: A semiconductor structure includes a semiconductor substrate, first to third isolation structures, and a conductive feature. The first to third isolation structures are over the semiconductor substrate and spaced apart from each other. The semiconductor substrate comprises a region surrounded by a sidewall of the first isolation structure and a first sidewall of the second isolation structure. The conductive feature extends vertically in the semiconductor substrate and between the between the second and third isolation structures, wherein the conductive feature has a rounded corner adjoining a second sidewall of the second isolation structure opposite the first sidewall of the second isolation structure.

Abstract: A drive device includes a housing, a motor and a transmission assembly; the housing includes a first casing and a second casing; the first casing includes a first protruding portion and a second protruding portion; the second casing includes a third protruding portion; the transmission assembly includes a first-stage worm, a second-stage worm and a transmission wheel; the first-stage worm includes a first tooth-shaped portion; the second-stage worm includes a second tooth-shaped portion; the first protruding portion and the second protruding portion both limitedly cooperate with the second-stage worm; along the axial direction of the second tooth-shaped portion, the first protruding portion is located on one side of the second tooth-shaped portion; the second protruding portion is located on the other side of the second tooth-shaped portion; and the distance between the third protruding portion and the transmission wheel is within a preset range.

Abstract: A fluid control assembly and a fluid control device are provided. The fluid control assembly includes a valve body component and a valve core component. At least part of the valve core component is located in a valve cavity. The valve body component is provided with a body portion and a protruding portion. The body portion forms at least part of a wall portion of the valve cavity, and the protruding portion protrudes from the peripheral wall of the body portion. The fluid control assembly is provided with a first flow channel, and at least part of the first flow channel is located in the valve core component. The protruding portion is provided with two or more lugs, at least some of the lugs are provided with the second flow channels, and circulation ports of at least some of the second flow channels have the same orientation.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: A semiconductor device and method of fabricating the same include a substrate, a first epitaxial layer, a first protection layer, and a contact etching stop layer. The substrate includes a PMOS transistor region, and the first epitaxial layer is disposed on the substrate, within the PMOS transistor region. The first protection layer is disposed on the first epitaxial layer, covering surfaces of the first epitaxial layer. The contact etching stop layer is disposed on the first protection layer and the substrate, wherein a portion of the first protection layer is exposed from the contact etching stop layer.

Abstract: A semiconductor device includes a dielectric structure, a conductive structure disposed in the dielectric structure, a first dielectric feature disposed over the dielectric structure, a conductive element disposed in the first dielectric feature and connected to the conductive structure, and a barrier feature disposed around the conductive element and disposed outside of the conductive structure.

Abstract: A semiconductor structure includes a substrate, at least one gate electrode, a plurality of source/drain (S/D) regions, a backside contact, a first dielectric layer, and a conductive via. The at least one gate electrode is disposed in the substrate. The S/D regions is disposed in the substrate and laterally disposed aside the at least one gate electrode. The backside contact is disposed above the S/D regions and the at least one gate electrode. The first dielectric layer is disposed between the backside contact and the plurality of S/D regions and the at least one gate electrode. The conductive via is extended through the first dielectric layer to electrically connect the S/D regions and the backside contact. The conductive via includes an anisotropic transport material or a topological material.

Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: A semiconductor structure includes a semiconductor substrate, a transistor, a plurality of isolation structures, and a conductive feature. The transistor is over the semiconductor substrate. The isolation structures are over the semiconductor substrate. The isolation structures define a semiconductor ring of the semiconductor substrate surrounding the transistor. The conductive feature extends vertically in the semiconductor substrate and surrounds the transistor and semiconductor ring. The conductive feature has a rounded corner facing the semiconductor ring from a top view.

Abstract: A cross laser calibration device used to calibrate a tool center point is provided. The calibration device includes a coordinate orifice plate, a set of cross laser sensors and a rotational and translational movement mechanism. The coordinate orifice plate has an orifice center point. The set of cross laser sensors is arranged on the coordinate orifice plate to generate cross laser lines intersecting at the orifice center point. The set of cross laser sensors is driven by the second motor to rotate around the center point of the second motor, wherein the orifice center point has an off-axis setting relative to the center point of the second motor.

Abstract: A method includes: etching a trench on a surface of a substrate; filling the trench with a dielectric material to form a first isolation region; depositing a patterned mask layer on the substrate, the patterned mask layer comprising an opening exposing the substrate; implanting oxygen into the substrate through the opening to form an implant region; generating a second isolation region from the implant region; and forming a transistor on the substrate. The transistor includes a channel laterally surrounding the second isolation region.

Abstract: An electrolyte composition, quasi-solid-state electrolyte, and lithium-ion battery employing the same are provided. The electrolyte composition includes a component (A), component (B) and component (C). The component (A) is a combination of a first polymer (A1) and a second polymer (A2), or a third polymer (A3). The first polymer (A1) has a repeating unit of Formula (I), the second polymer (A2) has a repeating unit of Formula (II), and the third polymer (A3) has a repeating unit of Formula (I) and a repeating unit of Formula (II) , wherein R1, R2, R3, R4, R5, Z1, and Z3 are as defined in the specification. The component (B) is a lithium salt and the component (C) is a solvent.

Abstract: A semiconductor device includes a substrate and an interconnect layer disposed on the substrate. The interconnect layer includes a dielectric layer and an interconnect extending through the dielectric layer. The interconnect includes a bulk metal region and a single barrier/liner layer, which serves as both a barrier layer and a liner layer and which is disposed to separate the bulk metal region from the dielectric layer.

Abstract: A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.