Abstract: A semiconductor device including a substrate, a magnetic core and a conductor coil is provided. The magnetic core is disposed on the substrate, and formed by sub-layers of different materials stacked alternatively on one another. The conductor coil is disposed on the substrate, wherein the magnetic core partially extends to a level between an upper surface of the conductor coil and a bottom surface of the conductor coil.

Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: This invention relates to an iridium metal complex. The iridium metal complex comprises no more than three 1,3-dihydro-2H-benzo[d]imidazol-2-ylidene based carbene cyclometalate ligands. The iridium metal complex provides a blue emission. This is useful for organic light emitting diode (OLED) components where blue emitters have trailed behind the advances 5 of red and green emitters.

Abstract: A semiconductor structure including a first dielectric layer and a conductive pattern is provided. The conductive pattern is disposed in the first dielectric layer, wherein the conductive pattern comprises an alloy layer and a first conductive layer, the alloy layer surrounds sidewalls and a bottom surface of the first conductive layer, a material of the alloy layer comprises an alloy of at least two metals, and at least one of the at least two metals relative to the rest of the at least two metals tends to be reacted with a dielectric material of the first dielectric layer.

Abstract: An integrated circuit structure includes a semiconductor substrate, first and second source/drain features, a gate dielectric layer, a gate electrode, a field plate electrode, first and second metal silicide layers, a dielectric layer, and a spacer. The gate electrode and the field plate electrode are over the gate dielectric layer and respectively vertically overlapping a well region and a drift region in the semiconductor substrate. A first sidewall of the field plate electrode faces the gate electrode. The first and second metal silicide layers are over the gate electrode and the field plate electrode, respectively. The dielectric layer has a first portion between the gate electrode and the first sidewall of the field plate electrode and a second portion below a bottom surface of the field plate electrode. The spacer is alongside a second sidewall of the field plate electrode and over the second portion of the dielectric layer.

Abstract: A motor driving device includes a battery module and a conversion circuit. The conversion circuit drives a motor in a driving mode and charges the battery module in a charging mode. The conversion circuit includes a determination circuit, a controller, and a first phase upper arm switch circuit. The first phase upper arm switch circuit includes a power switch and a transistor. First terminals, second terminal, and control terminals of both the power switch and the transistor are respectively coupled to a positive power supply terminal of the battery module, a first phase node, and the controller. In the charging mode, when a first phase voltage value located at the first phase node is greater than a battery voltage value located at the positive power supply terminal, the determination circuit notifies the controller to turn on the transistor.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: An integrated circuit structure includes a semiconductor substrate, a first source/drain feature, a second source/drain feature, a gate dielectric layer, a gate electrode, a field plate electrode, and a dielectric layer. The semiconductor substrate has a well region and a drift region therein. The first source/drain feature is in the well region. The second source/drain feature is in the semiconductor substrate. The drift region is between the well region and the second source/drain feature. The gate dielectric layer is over the well region and the drift region. The gate electrode is over the gate dielectric layer and vertically overlapping the well region. The field plate electrode is over the gate dielectric layer and vertically overlapping the drift region. The dielectric layer is between the gate electrode and the field plate electrode. A top surface of the gate electrode is free of the dielectric layer.

Abstract: A wireless charging system is provided. The wireless charging system includes a wireless power supply platform, a first device, and a second device. The wireless power supply platform provides a wireless suppling power. The first device includes a first power receiving circuit, a first power switch, and a first control circuit. The second device includes a second power receiving circuit, a second power switch, and a second control circuit. The second control circuit communicates with the first control circuit to determine a coordinated switching state of the first power switch and the second power switch. The coordinated switching state determines a first output voltage value generated by the first power receiving circuit according to the wireless suppling power and a second output voltage value generated by the second power receiving circuit according to the wireless suppling power.

Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.

Abstract: An LDMOS transistor device includes a stepped isolation structure over a substrate, a gate electrode disposed over a portion of the stepped isolation structure, a source region disposed in the substrate, and a drain region disposed in the substrate. The stepped isolation structure includes a first portion having a first thickness, and a second portion having a second thickness greater than the first thickness. The second portion includes dopants. The drain region is adjacent to the stepped isolation structure.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a source region and a drain region arranged over and/or within a substrate. Further, a shallow trench isolation (STI) structure is arranged within the substrate and between the source and drain regions. A gate electrode is arranged over the substrate, over the STI structure, and between the source and drain regions. A portion of the gate electrode extends into the STI structure such that a bottommost surface of the portion of the gate electrode is arranged between a topmost surface of the STI structure and a bottommost surface of the STI structure.

Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

Abstract: A driving device and a driving method for driving a motor of an electric auxiliary vehicle are provided. The driving device includes a battery module, a transducer, a control circuit. The battery module stores a driving power. When an acceleration command is received, the control circuit controls the transducer to enter a first mode. In the first mode, the transducer provides the driving power to the motor. When a brake command is received, the control circuit controls the transducer to enter a second mode. In the second mode, the transducer provides an inductive power generated by the motor to the battery module. When the acceleration and brake commands are not received and a user does not apply an acceleration force to the electric auxiliary vehicle, the control circuit controls the transducer to enter a third mode. In the third mode, the transducer provides the inductive power to the battery module.

Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.

Abstract: A holding device applied to a cutting apparatus to hold an object to be cut includes a holding element and a plurality of damping particles. The holding element is used for holding the object to be cut, and the holding element includes at least one accommodating cavity. Each accommodating cavity extends inward from the outer surface of the holding element to form an accommodating space. The plurality of damping particles is placed in at least one accommodating cavity. During the cutting process of the object to be cut, the plurality of damping particles generates collision and friction with each other or with the cavity wall of the accommodating cavity to reduce the vibration generated by the object to be cut, thereby reducing the surface warpage of a plurality of small-volume objects formed after cutting the object to be cut.

Abstract: Technology is disclosed for transferring money anonymously between a sender and a recipient by use of a one-time use token. The method includes generating a one-time use token account for association with a one-time use token. The method includes generating the token and providing the token to the sender device in a machine-readable and transferable format. The method includes receiving a request to charge the one-time use token account after the token has been provided to the recipient device as a form of payment for a transaction. The method includes determining that an amount of the transaction is less than an amount of funds associated with the token and that the time of the transaction is within a time period for the use of the token. The method includes facilitating a transfer to the recipient account and deducting the amount of the transaction from a sender account.

Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.