Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.

Abstract: A platinum complex having at least one carbene fragment, and an OLED using the same are described. The platinum complex contains a platinum cation, a zero-valent nitrogen-containing heterocyclic bidentate chelate, and a dianionic nitrogen-containing heterocyclic bidentate chelate. The zero-valent nitrogen-containing heterocyclic bidentate chelate has at least one carbene unit coordinating to platinum. The dianionic nitrogen-containing heterocyclic bidentate chelate has at least one electron-withdrawing substituent, and forms two N—Pt bonds, or one N—Pt bond and one C—Pt bond, with the central platinum cation.

Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.

Abstract: An iridium complex and an OLED using the same are shown. The iridium complex is represented by formula (I), wherein R1 is substituted or unsubstituted C1-12 alkyl, or substituted or unsubstituted C6-12 aryl; R2 is hydrogen, fluorine or —CmF2m+1 (m=1, 2 or 3), substituted or unsubstituted C1-12 alkyl, or substituted or unsubstituted C6-12 aryl; R3 is hydrogen, fluorine or —CmF2m+1 (m=1, 2 or 3), substituted or unsubstituted C1-6 alkyl or alkoxy, and n is 1, 2, 3 or 4; each of R4 is hydrogen or substituted or unsubstituted C1-12 alkyl, or R4's may join to form a C3-8 aromatic ring, and R4's may be the same or different; X1, X2, X3 and X4 are each independently CH or nitrogen; Y1, Y2 and Y3 are each independently carbon or nitrogen, with a proviso that at least one of Y1, Y2 and Y3 is nitrogen, and the tridentate chelate Y1^Y2^Y3 is dianionic.

Abstract: A method for manufacturing embedded memory using high-?-metal-gate (HKMG) technology is provided. A gate stack is formed on a semiconductor substrate. The gate stack comprises a charge storage film and a control gate overlying the charge storage film. The control gate includes a first material. A gate layer is formed of the first material, and is formed covering the semiconductor substrate and the gate stack. The gate layer is recessed to below a top surface of the gate stack, and subsequently patterned to form a select gate bordering the control gate and to form a logic gate spaced from the select and control gates. An ILD layer is formed between the control, select, and logic gates, and with a top surface that is even with top surfaces of the control, select, and logic gates. The control, select, or logic gate is replaced with a new gate of a second material.

Abstract: Techniques and arrangements for managing risk of fraudulent transactions made by a point-of-sale (POS) device operating in an online and an offline mode. In some instances, a payment service may maintain a merchant profile with a list of merchant specific criteria. The payment service may encrypt and send the merchant specific criteria to the POS device associated with the merchant. The encrypted data may include a list of payment instruments used in previous successful transactions, customer transaction histories, and other customer information. The POS device may determine, upon receiving a payment instrument identifier in a transaction, whether the payment instrument has been used in a previous successful transaction. If the POS device determines the payment instrument has been used, it may process the transaction. If not, the POS device may warn the merchant that the transaction is a high-risk transaction.

Abstract: An iridium complex and an OLED using the same are provided. The iridium complex is represented by general formula (I). In the general formula (I), A1, A2, A3, A4 and A5 are each independently a 5-membered unsaturated ring or a 6-membered unsaturated ring.

Abstract: An iridium complex and a nitrogen-containing tridentate ligand are provided. The iridium complex is represented by below formula: wherein R1 and R1? are each independently substituted or unsubstituted C1-C12 alkyl, substituted or unsubstituted C6-C12 aryl, or —CmF2m+1, m is an integer of 0 to 3; R2 and R2? are each independently hydrogen, substituted or unsubstituted C1-C12 alkyl, or substituted or unsubstituted C6-C12 aryl; p and p? are each independently 0 or 1; R3, R3?, R4 and R4? are each independently hydrogen, fluorine, substituted or unsubstituted C1-C12 alkyl, substituted or unsubstituted C1-C6 alkoxyl, or substituted or unsubstituted C6-C12 aryl; q and q? are each independently an integer of 0 to 3; r and r? are each independently an integer of 0 to 4; X1 to X7 are each independently carbon or nitrogen; A is —O—, —CH2—, or —CR2—, R is methyl, ethyl, or propyl; and a is 0 or 1.

Abstract: A platinum complex, an OLED and an apparatus for providing visible emission or near-infrared (NIR) emission using the same are described. The platinum complex has a structure represented by formula (I): wherein A1 to A4 each independently represent a 5-membered or 6-membered unsaturated ring, a first chelating ligand including A1 and A4 fragments has a minus one formal charge, and a second chelating ligand including A2 and A3 fragments has a minus one formal charge.

Abstract: An organic compound with a tetrahedral-like geometry is disclosed. The organic compound has a structure represented by formula (I): wherein A1 to A4 each independently represent a 5-membered or 6-membered unsaturated ring; B1 represents direct bonding, —C—, —O—, —N—, —S— or —C?C—; m is 0 or 1; each of Ra's is independently hydrogen, fluorine, oxygen, substituted or unsubstituted C1-C12 alkyl or substituted or unsubstituted C6-C12 aryl; and n is an integer of 0 to 2.

Abstract: Organometallic compounds, organic light-emitting devices, and lighting devices employing the same are provided. The organometallic compound has a chemical structure represented by formula (I) or (II): wherein n is 1 or 2; each R1 is independent and can be hydrogen, C1-8 alkyl, C1-8 alkoxy, C5-10 aryl, or C2-8 heteroaryl; each R2 is independent and can be hydrogen, C1-8 fluoroalkyl, or C1-8 alkyl; A is N, or CH; B is N, or CH; D is N, or C—R3, wherein R3 is H, or C1-8 alkyl; and R1 is not hydrogen when R2 is hydrogen.

Abstract: A platinum complex, an OLED using the platinum complex, and an apparatus emitting visible light or near-IR light are provided. The platinum complex has a structure represented by formula (I): wherein A1 to A3 are each independently a six-membered ring or a five-membered ring; R1 is substituted or unsubstituted C1-C12 alkyl or substituted or unsubstituted C6-C12 aryl; each R2 is independently hydrogen, substituted or unsubstituted C1-C12 alkyl, or substituted or unsubstituted C1-C6 alkoxy; p is an integer of 1 to 2; when p is equal to 2, two R2's can be joined to form a C3-C8 aromatic ring; and a first chelating ligand having A1 and a carbene fragment has a minus one formal charge and a second chelating ligand having A2 and A3 has a minus one formal charge.

Abstract: An iridium complex and a nitrogen-containing tridentate ligand are provided. The iridium complex is represented by below formula: wherein R1 and R1? are each independently substituted or unsubstituted C1-C12 alkyl, substituted or unsubstituted C6-C12 aryl, or —CmF2m+1, m is an integer of 0 to 3; R2 and R2? are each independently hydrogen, substituted or unsubstituted C1-C12 alkyl, or substituted or unsubstituted C6-C12 aryl; p and p? are each independently 0 or 1; R3, R3?, R4 and R4? are each independently hydrogen, fluorine, substituted or unsubstituted C1-C12 alkyl, substituted or unsubstituted C1-C6 alkoxyl, or substituted or unsubstituted C6-C12 aryl; q and q? are each independently an integer of 0 to 3; r and r? are each independently an integer of 0 to 4; X1 to X7 are each independently carbon or nitrogen; A is —O—, —CH2—, or —CR2—, R is methyl, ethyl, or propyl; and a is 0 or 1.

Abstract: A method for modular display frame is provided. The method includes the following steps. A number of display devices are combined to form a composite screen. A directional code including a number of positioning marks is displayed on each display device. The directional code displayed on each display device is scanned. Orientation information of each display device is obtained. A unique pattern is displayed on each display device. The composite screen is captured to generate a first image. Spatial location information of each display device is obtained from the first image. A number of display parameters corresponding to the display devices are calculated according to the orientation information and the spatial location information of the display devices. The display parameters are transmitted to the display devices. Each display device displays a regional frame according to the display parameters of the corresponding display device.

Abstract: A method for manufacturing a memory device includes forming trenches in a substrate to define an active region, filling an insulation material in the trenches, treating at least one portion of the insulation material, removing an upper portion of the insulation material from the trenches, so as to expose upper portions of side surfaces of the active region and to convert remaining portions of the insulation material in the trenches to shallow trench isolation (STI) disposed on opposite sides of the active region, forming a lower oxide layer, a middle charge trapping layer, and an upper oxide layer which cover the exposed upper portions of the side surfaces of the active region, an upper surface of the active region between the side surfaces of the active region, and the STI, and forming a gate layer on the upper oxide layer.

Abstract: A method for manufacturing a memory device includes forming trenches in a substrate to define an active region, filling an insulation material in the trenches, treating at least one portion of the insulation material, removing an upper portion of the insulation material from the trenches, so as to expose upper portions of side surfaces of the active region and to convert remaining portions of the insulation material in the trenches to shallow trench isolation (STI) disposed on opposite sides of the active region, forming a lower oxide layer, a middle charge trapping layer, and an upper oxide layer which cover the exposed upper portions of the side surfaces of the active region, an upper surface of the active region between the side surfaces of the active region, and the STI, and forming a gate layer on the upper oxide layer.

Abstract: A power conversion apparatus and a protection method of the power conversion apparatus while a feedback current signal of the power conversion apparatus is abnormal are provided. The protection method includes a step of stopping switching a power switch if a duty cycle of a pulse width modulation signal is continuously greater than a preset duty cycle for at least one signal cycle and a voltage of a current sensing signal is smaller than a preset voltage level during the at least one signal cycle.

Abstract: An iridium complex and an OLED using the same are shown. The iridium complex is represented by formula (I), wherein R1 is substituted or unsubstituted C1-12 alkyl, or substituted or unsubstituted C6-12 aryl; R2 is hydrogen, fluorine or —CmF2m+1 (m=1, 2 or 3), substituted or unsubstituted C1-12 alkyl, or substituted or unsubstituted C6-12 aryl; R3 is hydrogen, fluorine or —CmF2m+1 (m=1, 2 or 3), substituted or unsubstituted C1-6 alkyl or alkoxy, and n is 1, 2, 3 or 4; each of R4 is hydrogen or substituted or unsubstituted C1-12 alkyl, or R4's may join to form a C3-8 aromatic ring, and R4's may be the same or different; X1, X2, X3 and X4 are each independently CH or nitrogen; Y1, Y2 and Y3 are each independently carbon or nitrogen, with a proviso that at least one of Y1, Y2 and Y3 is nitrogen, and the tridentate chelate Y1?Y2?Y3 is dianionic.

Abstract: A platinum complex represented by general formula (I) or general formula (II) and an organic light-emitting diode using the same are provided. In general formulae (I) and (II), L1 and L2 are nitrogen-containing heterocyclic bidentate ligands; R1 is a substituted or unsubstituted C1-C12 alkyl group, or a substituted or unsubstituted C6-C12 aryl group; R2 is hydrogen, halogen, a substituted or unsubstituted C1-C12 alkyl group, or a substituted or unsubstituted C6-C12 aryl group; R3 is hydrogen, a substituted or unsubstituted C1-C12 alkyl group, or a substituted or unsubstituted C6-C12 aryl group; RF is —CmF2m+1, m is an integer of 1 to 3; X1 to X6 are independently carbon or nitrogen; provided that when X6 is nitrogen and X3, X4, and X5 are carbon, R3 is not hydrogen.

Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.