Abstract: Disclosed herein is a hinge antibody capable of being selectively activated in a target cell or tissue to treat a condition therein. The hinge antibody includes a functional antibody, two inhibitory domains and four cleavable linkers. The functional antibody is capable of treating the condition in an activated state, and has two light chains and two heavy chains. Each inhibitory domain includes a hinge domain of an immunoglobulin and consists of two peptide arms. Each cleavable linker includes a peptide substrate cleavable by an enzyme specifically or highly expressed in the target cell or tissue, and connects one of the peptide arms of the inhibitory domains to the N-terminal of one of the light chains and heavy chains of the functional antibody. Also disclosed herein are methods for preparing and using this hinge antibody.

Abstract: A memory device includes a semiconductor substrate, a logic transistor, and a storage transistor. The semiconductor substrate has a logic region and a memory region. The logic transistor is disposed on the logic region, in which the logic transistor comprises a high-k metal gate structure. The storage transistor is disposed on the memory region, in which the storage transistor includes a charge storage structure and a high-k metal gate structure. The charge storage structure is disposed on the memory region. The high-k metal gate structure is disposed on the charge storage structure.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a semiconductor substrate, well regions, logic transistors, a high-voltage transistor, and a storage transistor. The well regions are disposed in the semiconductor substrate and include logic well regions, a high-voltage well region, and a memory well region. The logic transistors are disposed on the logic well regions. Each the logic transistors includes a high-k metal gate structure. The storage transistor is disposed on the memory well region, and includes a charge storage structure and a high-k metal gate structure. In the method for fabricating the memory device, a high-k first process or high-k last process is used for the formation of the high-k metal gate structures of the memory device. Because all the logic transistors and the storage transistor are formed with the high-k metal gate structure, a number of masks is decreased.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

Abstract: A flame retardant is provided, which has a structure represented by the following Structural Formula (I) or (II): wherein R1 and R2 each independently represent a substituted or unsubstituted aromatic group, a substituted or unsubstituted araliphatic group, a substituted or unsubstituted aliphatic group, or a substituted or unsubstituted cycloaliphatic group; R2 is R2N?C?N—R5m, wherein R5 is arylene or alkylene, and is identical or different in the repeat unit, and m is an integer from 0 to 5; n is an integer equal to or larger than 1; “” and “” respectively represent either a double bond or two single bonds, and “” and “” are not both double bonds; when “” represents a double bond, R3 is an oxygen atom; when “” represents two single bonds, R3 is R3a and R3b, in which R3a is a hydroxyl group and R3b is when “” represents a double bond, R4 is a nitrogen atom; when “” represents two single bonds, R4 is R4a and R4b, in which R4a is a secondary amino group and R4b is and R2? is attached to R4a

Abstract: An iridium complex and an OLED using the same are provided. The iridium complex is represented by general formula (I). In the general formula (I), A1, A2, A3, A4 and A5 are each independently a 5-membered unsaturated ring or a 6-membered unsaturated ring.

Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.

Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.

Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.

Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.

Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.

Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a semiconductor substrate, well regions, logic transistors, a high-voltage transistor, and a storage transistor. The well regions are disposed in the semiconductor substrate and include logic well regions, a high-voltage well region, and a memory well region. The logic transistors are disposed on the logic well regions. Each the logic transistors includes a high-k metal gate structure. The storage transistor is disposed on the memory well region, and includes a charge storage structure and a high-k metal gate structure. In the method for fabricating the memory device, a high-k first process or high-k last process is used for the formation of the high-k metal gate structures of the memory device. Because all the logic transistors and the storage transistor are formed with the high-k metal gate structure, a number of masks is decreased.