Abstract: The comparison device includes a first through second comparators, a chop switching unit, a delta-sigma modulation unit, and a first through second compensation units. The chop switching unit transmits a first and a second signals to two input terminals of the first comparator during a first period, and inverses the first and second signals during a second period. The delta-sigma modulation unit compares the comparison results of two parallel comparators and generates the digital control codes for the comparators with the awareness of the chop switching unit. The first and the second compensation units adjust the threshold voltages of the comparators according to the digital control codes and a step size for calibrating the offset voltages of two comparators. The calibration scheme requiring no assumption on the input signal statistics is background thus the comparison device will not interrupt normal operation and is immune to PVT variations.

Abstract: The present invention relates to a DVD-holding case having a disk-holding tray on the inner side of a bottom housing thereof. The tray includes two projecting ears at opposing sides thereof. The projecting ears are resiliently and inclinedly formed on the bottom housing with a raised outer side thereof, having a hole for receiving a finger. The outer side of the hole is provided with an incline on which the finger leans while the opposing side thereof extends to the top of the supporting rim of the tray. In addition, an engaging member is respectively formed at two sides of either projecting ear, extending to the top of the supporting rim of the tray, thereby engaging the disk. When the disk is held by fingers in the hole, the projecting ears are depressed while the disk is simultaneously released from the engaging member, thereby reaching the effect of easy removal without scratching or bending the disk.

Abstract: A gain enhanced cascoded CMOS amplifier includes: a cascading transistor having its source connected to a folding point node, its drain connected to a first amplifier output terminal, and a gate, the folding point node being coupled to a first power supply terminal; a gain enhancing circuit having a negative input terminal coupled to the first folding point node, a positive input terminal responsive to a first reference voltage source, and an output terminal coupled to the gate of the first cascoding transistor; a first output coupling circuit coupling the first amplifier output terminal to a second power supply terminal; a first input transistor having a gate responsive to a first input voltage, a source, and a drain, the first input transistor having particular physical dimensions; and a first pole-isolating transistor having a drain connected to the first folding point node, a source connected to the drain of the first input transistor, and a gate responsive to an isolation bias voltage, the first pole iso