Abstract: A pixel structure including a substrate, a gate, a patterned dielectric layer, a semiconductor layer, a source, a drain and a reflective pixel electrode is provided. The gate is disposed on the substrate, whereon the patterned dielectric layer is disposed to cover the gate. The patterned dielectric layer has a plurality of bumps and at least one opening; the bumps are disposed on the substrate exposed by the opening and the semiconductor layer is disposed on the patterned dielectric layer above the gate. The source and the drain are disposed on the semiconductor layer. The reflective pixel electrode is disposed on the patterned dielectric layer to cover the bumps and electrically connected with the drain. Hence, the pixel structure can achieve better reliability.

Abstract: A method for manufacturing a bottom substrate of a liquid crystal display device by using only three masks is disclosed. The method includes the following steps. First, a patterned first metal layer, an insulating layer, a semiconductor layer and a second metal layer are formed subsequently on a substrate. Afterwards, the second metal layer is manufactured to have two different thicknesses by using a photolithographic process. After that, a planar layer is formed on the second metal layer and then the planar layer is etched until part of the second metal layer is exposed. Finally, a patterned transparent electrode layer is formed on the second metal layer.

Abstract: A method of fabricating a thin film transistor is provided. A gate is formed on a substrate. Then, an insulating layer is formed on the substrate to cover the gate. A semiconductor layer is formed on the insulating layer above the gate. A source/drain is formed on the semiconductor layer. After forming the source/drain, a surface treatment process is performed.

Abstract: A pixel structure including a substrate, a gate, a patterned dielectric layer, a semiconductor layer, a source, a drain and a reflective pixel electrode is provided. The gate is disposed on the substrate, whereon the patterned dielectric layer is disposed to cover the gate. The patterned dielectric layer has a plurality of bumps and at least one opening; the bumps are disposed on the substrate exposed by the opening and the semiconductor layer is disposed on the patterned dielectric layer above the gate. The source and the drain are disposed on the semiconductor layer. The reflective pixel electrode is disposed on the patterned dielectric layer to cover the bumps and electrically connected with the drain. Hence, the pixel structure can achieve better reliability.

Abstract: A pixel structure including a substrate, a gate, a dielectric layer, a semiconductor layer, a plurality of semiconductor bumps, a source, a drain and a reflective pixel electrode is disclosed. The gate is disposed on the substrate. The dielectric layer is disposed on the substrate and covers the gate. The semiconductor layer is disposed on the dielectric layer over the gate. The semiconductor bumps are disposed on the dielectric layer. The source and drain are disposed on the semiconductor layer. The reflective pixel electrode covering the semiconductor bumps is disposed on the dielectric layer and electrically connected to the drain.

Abstract: A lower substrate for a liquid crystal display device and the method of making the same are disclosed. The method includes steps of: (a) providing a substrate; (b) forming a patterned transparent layer having plural recess on the substrate; (c) forming a first barrier layer on the surface of the recess; (d) coating a first metal layer on the first barrier layer and making the surfaces of the first metal layer and the transparent layer in substantially the same plane; and (e) forming a first insulated layer and a semi-conductive layer in sequence. The method further can optionally comprise the steps of: (f) forming a patterned second metal layer, wherein part of the semi-conductive layer is exposed, thus forming the source electrode and the drain electrode; and (g) forming a transparent electrode layer on part of the transparent layer and part of the second metal layer.

Abstract: A method for manufacturing a substrate of a liquid crystal display device is disclosed. The method includes forming a conductive line structure with low resistance to improve the difficulty of the resistance matching. The method can effectively reduce the resistance of the conductive line of the LCD panel to increase the transmission rate of the driving signal. Hence, the increasing yield of products can reduce the cost of manufacturing, and can meet the requirement of the large-size and high-definition thin film transistor liquid crystal display device.

Abstract: A manufacturing method for a pixel structure is provided. The method includes the following steps. A first photomask is used to form a source/drain on a substrate. A second photomask is used twice to form a transparent conductive layer and a channel layer on the substrate respectively. The transparent conductive layer covers a portion of the source/drain and is electrically connected with the same, and the pattern of the transparent conductive layer and the pattern of the channel layer are complementary patterns. Then, a dielectric layer is formed over the substrate to cover the transparent conductive layer and the channel layer. A third photomask is used to form a gate on the dielectric layer.

Abstract: A method, system and scan lens for use therein are provided for high-speed, laser-based, precise laser trimming at least one electrical element along a trim path. The method includes generating a pulsed laser output with a laser, the output having one or more laser pulses at a repetition rate. A fast rise/fall time, pulse-shaped q-switched laser or an ultra-fast laser may be used. Beam shaping optics may be used to generate a flat-top beam profile. Each laser pulse has a pulse energy, a laser wavelength within a range of laser wavelengths, and a pulse duration. The wavelength is short enough to produce desired short-wavelength benefits of small spot size, tight tolerance, high absorption and reduced or eliminated heat-affected zone (HAZ) along the trim path, but not so short so as to cause microcracking. In this way, resistance drift after the trimming process is reduced.

Abstract: A multi-mode power supply device of a wireless earphone is disclosed. The earphone is communicable bi-directionally with portable communication devices wirelessly through an antenna. The earphone has a battery set. In at least one side of the earphone; an internal of the earphone has a power management circuit. The battery set supplies power to the power management circuit. The power management circuit is used to control the power on or off. The communication devices are selected from portable mobile phones and vehicle used phones. A suspender is capable of being inserted into or buckled into the groove of the earphone so that the suspender is positioned at one side of the power supply module. The suspender has a power supply module. When the suspender is combined to the earphone. The power management circuit is electrically connected to the power supply module.

Abstract: A method for manufacturing a pixel structure is provided. A first conductive layer is formed on a substrate and patterned using a first mask to form a gate. A dielectric layer is formed over the substrate to cover the gate. A semiconductor material layer and a second conductive layer are sequentially formed over the dielectric layer. The second conductive layer is patterned using a second mask to form a pixel electrode. A patterned photo-resist layer is formed by using the first mask again such that the semiconductor material layer above the gate is protected. The semiconductor material layer is patterned to form a semiconductor layer using the pixel electrode and the patterned photo-resist layer as an etching mask. The patterned photo-resist layer is removed. A third conductive layer is formed and patterned to form a source/drain by using a third mask. The drain is electrically connected to the pixel electrode.

Abstract: A method for manufacturing a bottom substrate of a liquid crystal display device by using only three masks is disclosed. The method includes the following steps. First, a patterned first metal layer, an insulating layer, a semiconductor layer and a second metal layer are formed subsequently on a substrate. Afterwards, the second metal layer is manufactured to have two different thicknesses by using a photolithographic process. After that, a planar layer is formed on the second metal layer and then the planar layer is etched until part of the second metal layer is exposed. Finally, a patterned transparent electrode layer is formed on the second metal layer.

Abstract: A laser processing system implements a method for aligning a probe element (e.g., a probe pin) with a device interface element (e.g., a contact pad of a circuit substrate). First, the laser processing system generates an optical reference beam at one or more predetermined positions to calibrate a reference field. The laser processing system then detects a position of the probe element in the reference field. The laser processing system also determines a relative position of the device interface element in the reference field. Based on the position of the probe element and the device interface element, the laser processing system then initiates alignment of the probe element and the device interface element. In one application, alignment of the probe element and the device interface element further includes contacting the probe element to the device interface element to make an electrical connection.

Abstract: Disclosed is a bra with air bags for massaging breast and draining breast milk. The air bags are inhaled and exhausted with a warm pulse positive pressure air to procure a warm massage effect for breasts, and further the air bag gradually squeezes the breasts from bottom of the breasts to nipple for draining breast milk and collecting breast milk into a baby bottle.

Abstract: A structure applied to a photolithographic process is provided. The structure includes at least a film layer, an optical isolation layer, an anti-reflection coating and a photoresist layer sequentially formed over a substrate. In the photolithographic process, the optical isolation layer stops light from penetrating down to the film layer. Since the optical isolation layer is set up underneath the photoresist layer, light emitted from a light source during photo-exposure is prevented from reflecting from the substrate surface after passing through the film layer. Thus, the critical dimensions of the photolithographic process are unaffected by any change in the thickness of the film layer.

Abstract: A method, system and scan lens system are provided for high-speed, laser-based, precise laser trimming at least one electrical element. The method includes generating a pulsed laser output having one or more laser pulses at a repetition rate. Each laser pulse has a pulse energy, a laser wavelength within a range of laser wavelengths, and a pulse duration. The method further includes selectively irradiating the at least one electrical element with the one or more laser pulses focused into at least one spot having a non-uniform intensity profile along a direction and a spot diameter as small as about 6 microns to about 15 microns so as to cause the one or more laser pulses to selectively remove material from the at least one element and laser trim the at least one element while avoiding substantial microcracking within the at least one element.

Abstract: A structure applied to a photolithographic process is provided. The structure comprises at least a film layer, an optical isolation layer, an anti-reflection coating and a photoresist layer sequentially formed over a substrate. In the photolithographic process, the optical isolation layer stops light from penetrating down to the film layer. Since the optical isolation layer is set up underneath the photoresist layer, light emitted from a light source during photo-exposure is prevented from reflecting from the substrate surface after passing through the film layer. Thus, the critical dimensions of the photolithographic process are unaffected by any change in the thickness of the film layer.

Abstract: A subtractor is connected between a p-channel bandgap reference unit and an n-channel bandgap reference unit. The subtractor includes two NPN transistors connected to the p-channel bandgap reference unit, and two PNP transistors connected to the n-channel bandgap reference unit. The subtractor takes the difference of the two currents produced by the p-channel and n-channel bandgap reference units and generates a temperature insensitive and curvature-compensated reference voltage of less than one volt across an output resistor.

Abstract: A subtractor is connected between a p-channel bandgap reference unit and an n-channel bandgap reference unit. The subtractor includes two NPN transistors connected to the p-channel bandgap reference unit, and two PNP transistors connected to the n-channel bandgap reference unit. The subtractor takes the difference of the two currents produced by the p-channel and n-channel bandgap reference units and generates a temperature insensitive and curvature-compensated reference voltage of less than one volt across an output resistor.

Abstract: A method and system for high-speed, precise micromachining an array of devices are disclosed wherein improved process throughput and accuracy, such as resistor trimming accuracy, are provided. The number of resistance measurements are limited by using non-measurement cuts, using non-sequential collinear cutting, using spot fan-out parallel cutting, and using a retrograde scanning technique for faster collinear cuts. Non-sequential cutting is also used to manage thermal effects and calibrated cuts are used for improved accuracy. Test voltage is controlled to avoid resistor damage.