Abstract: A telescopic device includes a first U-shaped connector with a plurality sets of adjustment slots defined in two sides thereof and arranged along an adjustment direction; a second U-shaped connector defining first through holes in two sides thereof, the second U-shaped connector being inserted into the first U-shaped connector with U-shaped openings thereof opposite to each other to define an accommodating space; a first spring located in the accommodating space and abutting against the first and second U-shaped connectors, respectively; an elastic pin with two ends thereof extending through the first through holes and engaging into one of the plurality sets of adjustment slots; and an initial fixing pin being detachably connected to the first and second U-shaped connectors. A telescopic annular tunnel steel arch includes an upper arch, two lower arches and two telescopic devices connecting two ends of the upper arch to the two lower arches, respectively.

Abstract: Embodiments of the present application relate to functionalized N-acetylgalactosamine-analogs, methods of making, and uses of the same. In particular, mono or trivalent N-acetylgalactosamine analogs may be prepared by utilizing a wide variety of linkers containing functional groups. These functionalized N-acetylgalactosamine-analogs may be used in the preparation of targeted delivery of oligonucleotide-based therapeutics.

Abstract: A portable visual inspection apparatus comprises a box including a lower box portion and an upper box portion. The upper box portion defines a first accommodation space and is connected to the lower box portion such that is capable of being opened and closed. A visual inspection device is installed in the first accommodation space and is adapted to be switched between an expanded configuration in which the visual inspection device is at least partially expanded for photographing an image of an article, and a folded configuration in which the visual inspection device is at least partially folded for storage in the first accommodation space. A support platform is arranged in the lower box portion and defines an inspection area below the visual inspection device in the expanded configuration. The portable visual inspection apparatus is switchable between a use configuration and a transportation configuration.

Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a set of draw call instructions corresponding to a graphics workload, where the set of draw call instructions is associated with at least one run-time parameter. The apparatus may also obtain a first shader program associated with storing data in a system memory and at least one second shader program associated with storing data in a constant memory. Further, the apparatus may execute the first shader program or the at least one second shader program based on whether the at least one run-time parameter is less than or equal to a size of the constant memory. The apparatus may also update or maintain a configuration of a shader processor or a streaming processor based on executing the first shader program or the at least one second shader program.

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for fast incremental shared constants. In aspects, a CPU may determine/update shared constant data for a first draw call of a plurality of draw calls. The shared constant data, which may correspond to at least one shader, may be updated based on a draw call update for the first draw call. The CPU may communicate the updated shared constant data for the first draw call to a GPU. The GPU may receive, in at least one register, the updated shared constant data from the CPU and configure the at least one register based on the updated shared constant data corresponding to the draw call update of the first draw call of the plurality of draw calls.

Abstract: The present disclosure relates to methods and apparatus for graphics processing. For example, disclosed techniques facilitate improving bindless state processing at a graphics processor. Aspects of the present disclosure can receive, at a graphics processor, a shader program including a preamble section and a main instructions section. Aspects of the present disclosure can also execute, with a scalar processor dedicated to processing preamble sections, instructions of the preamble section to implement a bindless mechanism for loading constant data associated with the shader program. Additionally, aspects of the present disclosure can distribute the main instructions section and the constant data to a streaming processor for executing the shader program.

Abstract: Embodiments of the present application relate to functionalized N-acetylgalactosamine analogs, methods of making, and uses of the same. In particular, polyvalent N-acetylgalactosamine analogs may be prepared by utilizing a wide variety of linkers containing functional groups. These functionalized N-acetylgalactosamine analogs may be used in the preparation of targeted delivery of oligonucleotide-based therapeutics.

Abstract: A touch display substrate is provided, including a central touch area and a routing area located around the central touch area, where the routing area is provided with isolation lines and a plurality of touch signal lines led out from the central touch area, the extension direction of the isolation lines is parallel to the extension direction of the touch signal lines, the touch signal lines include first touch signal lines arranged close to the isolation lines and second touch signal lines arranged far from the isolation lines, and the width of the first touch signal lines is greater than the width of the second touch signal lines. A touch display device and a touch control signal line distribution method are provided.

Abstract: A method for reducing latency and increasing throughput in a reconfigurable computing system includes receiving a compute graph for execution on a reconfigurable dataflow processor comprising a grid of compute units and grid of memory units interconnected with a switching array. The compute graph includes a node specifying an operation on a tensor. The node may be split into multiple nodes that each specify the operation on a distinctive portion of the tensor to produce a first modified compute graph. The first modified compute graph may be executed. In addition, the multiple nodes may be within a single meta-pipeline stage and may be processed in parallel. Furthermore, the compute graph may further comprise a separate node for gathering the distinctive portions of the tensor into a complete tensor, to produce a second modified compute graph.

Abstract: A grating adjustment apparatus includes a first electrode layer, a second electrode layer and a first substrate and a second substrate that are opposite to each other; the grating adjustment apparatus further includes a plurality of first driving lines, a plurality of second driving lines and a plurality of grating units arranged in the first direction, and is configured as: when the grating adjustment apparatus is powered on, the grating unit is capable of forming a light transmission unit and a shading unit, and opening positions and/or opening ratios of the grating unit are adjustable; and the plurality of grating units are divided into at least one group; for the grating units in the same group, at least two of the first sub-electrodes are electrically connected to different first driving lines, and at least two of the second sub-electrodes are electrically connected to different second driving lines.

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for dynamic wave pairing. A graphics processor may allocate one or more GPU workloads to one or more wave slots of a plurality of wave slots. The graphics processor may select a first execution slot of a plurality of execution slots for executing the one or more GPU workloads. The selection may be based on one of a plurality of granularities. The graphics processor may execute, at the selected first execution slot, the one or more GPU workloads at the one of the plurality of granularities.

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for runtime optimization of the shader execution flow. A graphics processor may obtain instruction execution data associated with a graphics workload, the instruction execution data including graphics data for a set of shader operations. The graphics processor may configure, at a first iteration, at least one predication value based on the instruction execution data including the graphics data for the set of shader operations. The graphics processor may adjust, at a second iteration, an execution flow of the graphics workload based on the configured at least one predication value, the execution flow of the graphics workload including the set of shader operations. The graphics processor may execute or refrain from executing, at the second iteration, each of the set of shader operations based on the adjusted execution flow of the graphics workload.

Abstract: A touch display substrate is provided, including a central touch area and a routing area located around the central touch area, where the routing area is provided with isolation lines and a plurality of touch signal lines led out from the central touch area, the extension direction of the isolation lines is parallel to the extension direction of the touch signal lines, the touch signal lines include first touch signal lines arranged close to the isolation lines and second touch signal lines arranged far from the isolation lines, and the width of the first touch signal lines is greater than the width of the second touch signal lines. A touch display device and a touch control signal line distribution method are provided.

Abstract: The present disclosure relates to methods and apparatus for compute processing. For example, disclosed techniques facilitate improving performance of matrix multiplication in streaming processor. Aspects of the present disclosure can execute, with a load control unit, a first load instruction to load a set of input data of an input matrix from a first memory to a second memory. Aspects of the present disclosure can also execute, with the load control unit, a second load instruction to load a set of weight data of a weight matrix from the first memory to the second memory. Additionally, aspects of the present disclosure can perform, with an ALU component, a matrix multiplication operation using the set of input data and the set of weight data to generate an output matrix. Further, aspects of the present disclosure can store the output matrix at a general purpose register accessible to the ALU component.

Abstract: The present disclosure relates to methods and apparatus for graphics processing, e.g., a GPU. The apparatus may receive an image including a plurality of pixels associated with one or more workgroups and one or more pixel tiles, each of the workgroups and the pixel tiles including one or more pixels of the plurality of pixels. The apparatus may determine whether the one or more workgroups are misaligned with the one or more pixel tiles. The apparatus may determine a conversion order of the one or more workgroups when the one or more workgroups are misaligned with the one or more pixel tiles, the conversion order corresponding to a common multiple of one of the one or more workgroups and one of the one or more pixel tiles. The apparatus may convert each of the one or more workgroups based on the conversion order of the one or more workgroups.

Abstract: A data processing system includes an array of reconfigurable units and a compiler configured to generate a pipeline of n computational nodes related to a dataflow graph, interleaved between n+1 buffers on the array of reconfigurable units. Each computational node is coupled to perform calculations based on data received from an immediately preceding buffer of the n+1 buffers and store results of the calculations into an immediately following buffer of the n+1 buffers after a latency. The compiler is further configured to remove a buffer of the n+1 buffers from the pipeline based on a comparison of the latencies of the computational nodes. A corresponding method is also disclosed herein.

Abstract: The present disclosure relates to methods and apparatus for compute processing. For example, disclosed techniques facilitate improving performance of matrix multiplication in streaming processor. Aspects of the present disclosure can execute, with a load control unit, a first load instruction to load a set of input data of an input matrix from a first memory to a second memory. Aspects of the present disclosure can also execute, with the load control unit, a second load instruction to load a set of weight data of a weight matrix from the first memory to the second memory. Additionally, aspects of the present disclosure can perform, with an ALU component, a matrix multiplication operation using the set of input data and the set of weight data to generate an output matrix. Further, aspects of the present disclosure can store the output matrix at a general purpose register accessible to the ALU component.

Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a set of draw call instructions corresponding to a graphics workload, where the set of draw call instructions is associated with at least one run-time parameter. The apparatus may also obtain a first shader program associated with storing data in a system memory and at least one second shader program associated with storing data in a constant memory. Further, the apparatus may execute the first shader program or the at least one second shader program based on whether the at least one run-time parameter is less than or equal to a size of the constant memory. The apparatus may also update or maintain a configuration of a shader processor or a streaming processor based on executing the first shader program or the at least one second shader program.

Abstract: A computer-implemented method of transforming a high-level program for mapping onto a coarse-grained reconfigurable (CGR) processor with an array of CGR units, including sectioning a dataflow graph into a plurality of sections; extracting performance information for each of the plurality of sections; on a CGR unit: assigning to a section at least two computations dependent on a first data element; scheduling an additional load of the first data element in response to available memory bandwidth for that section; eliminating a buffer between the additional load of the first data element and one of the two computations, for that section; generating configuration data for the and communication channels, wherein the configuration data, when loaded onto an instance of the array of CGR units, causes the array of CGR units to implement the dataflow graph; and storing the configuration data in a non-transitory computer-readable storage medium.

Abstract: This disclosure provides systems, devices, apparatus and methods, including computer programs encoded on storage media, for GPR optimization in a GPU based on a GPR release mechanism. More specifically, a GPU may determine at least one unutilized branch within an executable shader based on constants defined for the executable shader. Based on the at least one unutilized branch, the GPU may further determine a number of GPRs that can be deallocated from previously allocated GPRs. The GPU may deallocate, for a subsequent thread within a draw call, the number of GPRs from the previously allocated GPRs during execution of the executable shader based on the determined number of GPRs to be deallocated.