Abstract: A cache memory die includes a substrate, a predetermined number of sets of memory cells on the substrate, a first set of input/output terminals on a first surface of the cache memory die, and a second set of input/output terminals on a second surface of the cache memory die. The first set of input/output terminals are connected to a primary memory circuit outside the cache memory die. A portion of the second set of input/output terminals are compatible with the first set of input/output terminals.

Abstract: An integrated circuit system having an interposer and an integrated circuit with first and second bond pads, the integrated circuit die bonded to the interposer using the first bond pads. The integrated circuit having circuit blocks, that operate at different operating voltages and voltage regulator modules die bonded to the second bond pads of the integrated circuit. The voltage regulator modules converting a power supply voltage to the operating voltage of a respective circuit block and supply the respective operating voltage to the circuit block via the second bond pads.

Abstract: A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row.

Abstract: The present disclosure relates to a method of routing probe pads to micro-bumps of an interposer. An interposer is provided having target micro-bumps and probe pads. The probe pads are initially unassigned. Target micro-bump locations and probe pad locations are obtained. Possible route assignments from the probe pads to the target micro-bumps are obtained. Costs are developed for the possible route assignments at least partially according to the target micro-bump locations and the probe pad locations. Final assignments are selected from the possible assignments according to the costs.

Abstract: Among other things, one or more systems and techniques for defining a group bounding box for related cells of an integrated circuit, and generating a new layout for the integrated circuit comprising the group bounding box are provided herein. That is, one or more group bounding boxes are defined based upon positional values of related cells. Such group bounding boxes are placed within the new layout based upon a placement technique, such as an objective function that takes into account wire length, timing, and cell density, for example. The one or more group bounding boxes are sized or reshaped to reduce cell overlap within the new layout. In this way, the new layout comprises related cells, bound by one or more group bounding boxes, that are placed within the new layout according to a configuration that mitigates wire length and timing delay of the integrated circuit.

Abstract: Among other things, one or more systems and techniques for defining a group bounding box for related cells of an integrated circuit, and generating a new layout for the integrated circuit comprising the group bounding box are provided herein. That is, one or more group bounding boxes are defined based upon positional values of related cells. Such group bounding boxes are placed within the new layout based upon a placement technique, such as an objective function that takes into account wire length, timing, and cell density, for example. The one or more group bounding boxes are sized or reshaped to reduce cell overlap within the new layout. In this way, the new layout comprises related cells, bound by one or more group bounding boxes, that are placed within the new layout according to a configuration that mitigates wire length and timing delay of the integrated circuit.

Abstract: An integrated circuit includes a process voltage temperature (PVT) effect transducer responsive to a PVT effect, a PVT effect quantifier coupled to the PVT effect transducer and configured to quantify the PVT effect to provide an output, and a bias controller configured to receive the output of the PVT effect quantifier and provide a bias voltage for a substrate of an NMOS or a PMOS transistor. The bias controller is configured to compare the output received from the PVT effect quantifier to a threshold value, and decrease or increase the bias voltage depending on whether the output is higher or lower than the threshold value.

Abstract: A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row.

Abstract: The present disclosure relates to a method of routing probe pads to micro-bumps of an interposer. An interposer is provided having target micro-bumps and probe pads. The probe pads are initially unassigned. Target micro-bump locations and probe pad locations are obtained. Possible route assignments from the probe pads to the target micro-bumps are obtained. Costs are developed for the possible route assignments at least partially according to the target micro-bump locations and the probe pad locations. Final assignments are selected from the possible assignments according to the costs.

Abstract: Methods and apparatus of performing floorplanning and routing for function blocks within a die and among multiple die are disclosed. Multiple die together with function blocks within each die may be represented by a flexible hierarchical (FH) tree. An initial floorplan for multiple die may be generated and hot spots between die or among function blocks within a die may be identified. Spacer blocks may be inserted between die, and block inflation may be performed, to remove hot spots. More perturbation of the block positions can be performed on the FH tree to rearrange the blocks and die. After the multiple die floorplanning, a plurality of micro bumps may be mapped to a plurality of pins of blocks of the plurality of die, placement and routing may be performed for the plurality of blocks within each die and connections for the plurality of dies.

Abstract: A substrate bias control circuit includes a process voltage temperature (PVT) effect transducer that responds to a PVT effect. A PVT effect quantifier is coupled to the PVT effect transducer. The PVT effect quantifier quantifies the PVT effect to provide an output. The PVT effect quantifier includes at least one counter and a period generator. The period generator provides a time period for the counter. A bias controller that is coupled to PVT effect quantifier is configured to receive the output of the PVT effect quantifier. The bias controller is configured to provide a bias voltage. The bias controller includes a bias voltage comparator.

Abstract: The present invention provides compositions comprising nucleic acids that target CSN5 gene expression and methods of using such compositions to silence CSN5 gene expression. More particularly, the present invention provides unmodified and chemically modified interfering RNA molecules which silence CSN5 gene expression and methods of use thereof, e.g., for treating cell proliferative disorders such as cancer. The present invention also provides nucleic acid-lipid particles that target CSN5 gene expression comprising an interfering RNA molecule, a cationic lipid, a non-cationic lipid, and optionally a conjugated lipid that inhibits aggregation of particles.

Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.

Abstract: The present application discloses a method of generating an intellectual property (IP) block design kit including an IP block circuit design and a system-level characteristics table for manufacturing an integrated circuit. According at least one embodiment, the IP block circuit design is generated. The IP block circuit design is simulated based on predetermined configuration sets, and each configuration set has manufacturing options and/or operating conditions. A plurality of system-level models for the predetermined configuration sets are generated based on the simulation of the IP block circuit design. The system-level characteristics table is generated by arranging the predetermined configuration sets and the system-level models in compliance with a system-level characteristics table template of a system-level characteristics modeling device. Then the IP block circuit design and the system-level characteristics table are stored as the IP block design kit.

Abstract: The present invention provides therapeutic nucleic acids such as interfering RNA (e.g., siRNA) that target the expression of genes associated with tumorigenesis and/or cell transformation, lipid particles (e.g., nucleic acid-lipid particles) comprising one or more (e.g., a cocktail) of the therapeutic nucleic acids, methods of making the lipid particles, and methods of delivering and/or administering the lipid particles, e.g., for the treatment of a cell proliferative disorder such as cancer.

Abstract: A probe card includes a plurality of probe pins, and a switch network connected to the plurality of probe pins. The switch network is configured to connect the plurality of probe pins in a first pattern, and reconnect the plurality of probe pins in a second pattern different from the first pattern.

Abstract: An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer.

Abstract: A method of designing an integrated circuit includes providing an integrated circuit design including a power network. A voltage drop mitigation system is provided, which includes a power strap enhancer configured to automatically find a source node and a terminal node in the power network. A redundant strap for the power network using the voltage drop mitigation system is added, wherein the redundant strap interconnects the source node and the terminal node. After the step of adding the redundant strap, dummy patterns may be added.

Abstract: A master-slave retention flip-flop includes a master latch adapted to latch an input data signal and to output a latched master latch data signal based on an input clock signal, a slave latch coupled to an output of the master latch and adapted to output a latched slave latch data signal based on the input clock signal, and a retention latch embedded within one of the master and slave latches adapted to preserve data in a power down mode based on a power down control signal.

Abstract: The present invention provides compositions comprising nucleic acids that target CSN5 gene expression and methods of using such compositions to silence CSN5 gene expression. More particularly, the present invention provides unmodified and chemically modified interfering RNA molecules which silence CSN5 gene expression and methods of use thereof, e.g., for treating cell proliferative disorders such as cancer. The present invention also provides nucleic acid-lipid particles that target CSN5 gene expression comprising an interfering RNA molecule, a cationic lipid, a non-cationic lipid, and optionally a conjugated lipid that inhibits aggregation of particles.