Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.

Abstract: An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer.

Abstract: A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row.

Abstract: A package structure includes a networking unit including a plurality of switches/routers and a plurality of network interface units coupled to the plurality of switches/routers, and an interposer including a plurality of metal connections. The interposer is substantially free from functional elements built therein. A functional element is outside of, and bonded onto, the interposer, wherein the functional element is electrically coupled to the networking unit through the plurality of metal connections.

Abstract: A partition method includes sorting the plurality of components into a plurality of partitions according to a set of partition criteria and sorting the plurality of components of each partition into a first stack and a second stack according to a set of stack criteria, and the first stack includes a plurality of higher pitch metal layers and the second stack includes a plurality of lower pitch metal layers. The partition criteria include size, power and speed of the component, and the stack criteria include a pitch of a metal layer.

Abstract: A method of forming a wafer on wafer (WOW) stack includes forming a predetermined array of connecting elements on a surface of a first wafer, the first wafer including dies of a first type. The dies of the first type have a first functionality. The method further includes bonding a second wafer to the first wafer using the predetermined array of connecting elements, the second wafer including dies of a second type. The dies of the second type have a separate functionality different from the first functionality. Bonding the second wafer to the first wafer comprises bonding an integer number of dies of the second type to a corresponding die of the first type. A total area of the dies of the second type bonded to the corresponding die of the first type is less than or equal to an area of the corresponding die of the first type.

Abstract: An integrated circuit includes a first radio frequency interconnect (RFI) transceiver, a second RFI transceiver, a third RFI transceiver, a fourth RFI transceiver and a guided transmission medium. The first RFI transceiver is configured to transmit or receive a first data signal. The second RFI transceiver is configured to transmit or receive a second data signal. The third RFI transceiver is configured to transmit or receive the first data signal. The fourth RFI transceiver is configured to transmit or receive the second data signal. The guided transmission medium is configured to carry the first data signal and the second data signal. The first RFI transceiver and the second RFI transceiver are connected to the third RFI transceiver and the fourth RFI transceiver by the guided transmission medium.

Abstract: In some embodiments, in a method performed by at least one processor for estimating an overall power state coverage of an electronic system level (ESL) model comprising a plurality of blocks for a module, a first value and a second value are set for each block of said plurality of blocks. At least one verification case is selected for each block in the ESL model. For each verification case of said at least one verification case: (a) a target coverage value is set, (b) a register transfer level (RTL) simulation is performed, (c) an actual coverage value is received, and (d) the first value or the second value is updated based on whether the actual coverage value is less than the target coverage value or not. A power state coverage is calculated for said each block. The overall power state coverage is calculated for the ESL model comprising said plurality of blocks for said module.

Abstract: A transceiver group includes a plurality of transceivers; wherein the transceiver group performs transmission and receiving through a wire, and each of the transceivers includes a transmitter and a receiver, and the transmitter includes: a carrier generator arranged to generate a plurality of carriers having different frequencies for a plurality of data streams to be transmitted; a modulator, coupled to the data streams to be transmitted and the carrier generator, to generate a plurality of modulated data streams carried on the plurality of carriers; and a summer arranged to merge the plurality of modulated data streams to an output signal to the wire; and the receiver includes: a carrier generator arranged to generate a plurality of carriers having different frequencies for an input signal received from the wire; and a demodulator, coupled to the input signal and the carrier generator, to generate a plurality of demodulated data streams.

Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.

Abstract: In some embodiments, in a method performed by at least one processor for estimating an overall power state coverage of an electronic system level (ESL) model comprising a plurality of blocks for a module, a first value and a second value are set for each block of said plurality of blocks. At least one verification case is selected for each block in the ESL model. For each verification case of said at least one verification case: (a) a target coverage value is set, (b) a register transfer level (RTL) simulation is performed, (c) an actual coverage value is received, and (d) the first value or the second value is updated based on whether the actual coverage value is less than the target coverage value or not. A power state coverage is calculated for said each block. The overall power state coverage is calculated for the ESL model comprising said plurality of blocks for said module.

Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.

Abstract: A cell layout, a cell layout library and a synthesizing method are disclosed. The cell layout includes a cell block and a tapping connector. The cell block has a pin. The pin being disposed at a Nth metal layer in the cell layout. The tapping connector is disposed at a (N+1)th metal layer and a (N+2)th metal layer and stacked above the pin of the cell block. The tapping connector is electrically connected to the pin and forms an equivalent tapping point of the pin of the cell block. N is a positive integer greater than or equal to 1.

Abstract: A method is disclosed that includes establishing an intellectual property (IP) bank, an application bank, and a technology bank; selecting valid configurations from the IP bank for corresponding IPs and at least one subsystem based on the application data, for generating in response to a user-defined requirement, by a model generator, a performance, power, area and cost (PPAC) model of the valid configurations; based on the PPAC model, creating at least one architecture comprising at least one of the corresponding IPs, and at least one of the valid configurations for the at least one of the corresponding IPs; and, estimating, by a PPAC explorer assessing the technology bank, at least one of a performance value, a power value, an area value and a cost value for a fabrication of the at least one architecture by simulating available fabrication process technology based on the technology bank.

Abstract: A method is disclosed that includes providing an IP bank, an application bank, and a technology bank; generating a hierarchical table based on the IP bank and the application bank; performing an estimation of at least one of a performance value, a power value, an area value and a cost value, which corresponds to the hierarchical table, by using the technology bank, to output an result data as a basis of fabrication of a system.

Abstract: A method of operating a memory circuit is disclosed. The memory circuit comprises a primary memory and a cache memory. The primary memory has P access channels of Q bits of channel bandwidth, and the cache memory has P subsets of Q*N memory cells, wherein P and Q are integers greater than 1, and N is a positive integer. The method includes determining, in response to a command for reading first and second data accessible through first and second access channels respectively, if a valid duplication of the first and second data is stored in the cache memory. If yes, the method further includes storing a duplication of Q*n bits of consecutively addressed data from each of the first and second access channels to the cache memory, n being an integer from 1 to N. Otherwise, the method further includes outputting the first and second data from the cache memory.

Abstract: A method of forming a wafer on wafer (WOW) stack includes forming a predetermined array of connecting elements on a surface of a first wafer, the first wafer including dies of a first type. The dies of the first type have a first functionality. The method further includes bonding a second wafer to the first wafer using the predetermined array of connecting elements, the second wafer including dies of a second type. The dies of the second type have a separate functionality different from the first functionality. Bonding the second wafer to the first wafer comprises bonding an integer number of dies of the second type to a corresponding die of the first type. A total area of the dies of the second type bonded to the corresponding die of the first type is less than or equal to an area of the corresponding die of the first type.

Abstract: A method includes (a) generating timing information of an integrated circuit (IC) floorplan by a processing unit, (b) displaying on a display device a representation of the IC floorplan according to the timing information, (c) receiving user input via an input device, the user input associated with an IC macro of the IC floorplan, (d) updating the timing information associated with the IC macro to generated updated timing information according to the user input, and (e) altering display of the representation according to the updated timing information.

Abstract: A method performed at least partially by a processor includes performing a test sequence. In the test sequence, a test pattern is loaded into a circuit. The test pattern is configured to cause the circuit to output a predetermined test response. A test response is unloaded from the circuit after a test wait time period has passed since the loading of the test pattern into the circuit. The unloaded test response is compared with the predetermined test response.

Abstract: Systems and methods for circuit fault diagnosis are provided. An original circuit design is evaluated to determine whether the original circuit design is to be modified based at least in part on one or more first faults. In response to the original circuit design being determined not to be modified based at least in part on the one or more first faults, a first test pattern set is automatically generated based at least in part on the original circuit design. The original circuit design is evaluated to determine whether the original circuit design is to be modified based at least in part on the first test pattern set. In response to the original circuit design being determined not to be modified based at least in part on the first test pattern set, fault testing is performed to determine whether the original circuit design fails.