Patents by Inventor Yun Han

Yun Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ELECTRONIC DEVICE AND METHOD FOR PROVIDING IP NETWORK SERVICE
    Publication number: 20160065686
    Abstract: An electronic device, according to one of the various embodiments of the present disclosure, includes: a memory; a communication module that transmits and receives messages; and a processor that, when a non-IP service-based message is received, creates an IP-based message including at least some of the non-IP service-based message, and provides the created IP-based message. In addition, various embodiments are provided.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 3, 2016
    Inventors: Dong-Hoo Park, Kyoung-Youp Park, Yun-Han Kim, Young-Man Park
  • IMAGE PROCESSING APPARATUS AND METHOD
    Publication number: 20160050350
    Abstract: An apparatus comprises an integrated circuit and at least one lens. The integrated circuit comprises an image sensor having a light sensing region. The light sensing region is partitioned into sub-regions. The integrated circuit also comprises a processor coupled with and beneath the image sensor. The processor is configured to generate a first processed image based on an image captured by one sub-region, and a second processed image based on another image captured by another sub-region. The first processed image and the second processed image are generated based on a pixel correction process executed by the processor which corrects one or more of the image or the another image based on a predefined light reception factor associated with the sub-regions. The image sensor is configured to receive light via the light sensing region through the at least one lens.
    Type: Application
    Filed: August 13, 2014
    Publication date: February 18, 2016
    Inventors: Sandeep Kumar GOEL, Yun-Han LEE, Ashok MEHTA
  • SLURRY SUPPLY DEVICE AND POLISHING APPARATUS INCLUDING THE SAME
    Publication number: 20160045999
    Abstract: Disclosed is a slurry supply device including a nozzle configured to eject slurry, a slurry supply unit configured to receive the slurry from the nozzle and to discharge the slurry through at least one slurry hole, a receiving unit configured to allow the slurry supply unit to be mounted, inserted, seated, coupled, supported, or placed therein so as to enable discharge of the slurry from the slurry supply unit, the receiving unit being configured to receive a flowing material around the slurry supply unit and a slurry protection unit configured to enclose a space for passage of the slurry from an exit of the nozzle to an entrance of the slurry supply unit in conjunction with the flowing material.
    Type: Application
    Filed: December 16, 2014
    Publication date: February 18, 2016
    Inventors: Jae Hyun Bae, Kee Yun Han
  • WAFER ON WAFER STACK METHOD OF FORMING AND METHOD OF USING THE SAME
    Publication number: 20160049435
    Abstract: A wafer on wafer (WOW) stack includes a first wafer having dies of a first type. The WOW stack further includes a second wafer bonded to the first wafer. The second wafer has dies of a second type. An integer number of dies of the second type are bonded to a corresponding die of the first type. A total area of the dies of the second type bonded to the corresponding die of the first type is less than or equal to an area of the corresponding die of the first type. A functionality of the dies of the first type is different from a functionality of the dies of the second type.
    Type: Application
    Filed: August 13, 2014
    Publication date: February 18, 2016
    Inventors: Sandeep Kumar GOEL, Yun-Han LEE
  • FUSE STRUCTURE
    Publication number: 20160035527
    Abstract: A fuse structure comprises a first conductive layer on a first level. The first conductive layer comprises a fuse line extending in a first direction. The fuse line has a first end portion, a second end portion opposite the first end portion, and a fuse link portion connecting the first end portion and the second end portion. The first conductive layer also comprises lines parallel to the fuse line, the lines being aligned in the first direction and being separated from one another by a first distance measured in the first direction. The fuse structure also comprises a second conductive layer on a second level different from the first level and coupled with the first conductive layer. The second conductive layer has parallel lines extending in a second direction, the parallel lines being separated by a second distance measured in a third direction orthogonal to the second direction.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 4, 2016
    Inventors: Chen-Ming HUNG, Yun-Han CHEN, Shao-Tung PENG, Shao-Yu CHOU, Yue-Der CHIH, Li-Chun TIEN
  • SYSTEM AND METHOD FOR DISPLAYING THREE-DIMENSIONAL MAP BASED ON ROAD INFORMATION
    Publication number: 20160025512
    Abstract: A system and method of displaying a three-dimensional (3D) map based on road information. A display system, including: a culling area determination unit to determine a culling area based on road information; a data conversion unit to convert data of at least a portion of objects displayed on the culling area; and a display unit to display at least the portion of the objects based on the converted data.
    Type: Application
    Filed: July 25, 2014
    Publication date: January 28, 2016
    Inventors: Jung Kak SEO, Yun Han Kim, Dae Myung Kim
  • PHYTASE FORMULATION
    Publication number: 20160007633
    Abstract: A liquid enzyme formulation, an enzyme granule formulation, methods for manufacturing enzyme granules using a fluid bed dryer, wherein the enzyme granules are thermostable without the need for a thermostable coating is provided. The enzyme granules are phytase granules used in the manufacturing of an animal feed, wherein the phytase granule is thermostable without the need for a thermostable coating and the phytase retains about 63% to about 134% of its activity after pelleting at 80° C.
    Type: Application
    Filed: March 10, 2014
    Publication date: January 14, 2016
    Inventors: Yun HAN, Michael PRATT, Yi WU
  • Compositions and methods for silencing genes expressed in cancer
    Patent number: 9222086
    Abstract: The present invention provides therapeutic nucleic acids such as interfering RNA (e.g., siRNA) that target the expression of genes associated with tumorigenesis and/or cell transformation, lipid particles (e.g., nucleic acid-lipid particles) comprising one or more (e.g., a cocktail) of the therapeutic nucleic acids, methods of making the lipid particles, and methods of delivering and/or administering the lipid particles, e.g., for the treatment of a cell proliferative disorder such as cancer.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: December 29, 2015
    Assignees: PROTIVA BIOTHERAPEUTICS, INC., THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY, DEPARTMENT OF HEALTH AND HUMAN SERVICES
    Inventors: Adam Judge, Yun-Han Lee, Ian MacLachlan, Snorri S. Thorgeirsson
  • Integrated semiconductor device and method for fabricating the same
    Patent number: 9224696
    Abstract: An integrated semiconductor device and method for fabricating the same are provided wherein the integrated semiconductor device comprises a substrate a first stress-inducing layer, a second stress-inducing layer and an integrated circuit layer. The first stress-inducing layer covers on the substrate. The second stress-inducing layer partially covers on the first stress-inducing layer. The integrated circuit layer is bonded over the substrate.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: December 29, 2015
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Shih-Wei Li, Yun-Han Chu, Guo-Chih Wei
  • RECIPROCAL DISTRIBUTION CALCULATING METHOD AND RECIPROCAL DISTRIBUTION CALCULATING SYSTEM FOR COST ACCOUNTING
    Publication number: 20150363891
    Abstract: Provided are a reciprocal distribution calculating method and a reciprocal distribution calculating system for cost accounting, in which, when performing cost accounting using a computer, a reciprocal distribution method is used to effectively perform cost accounting of each department. In the reciprocal distribution calculating method and the reciprocal distribution calculating system for cost accounting, reciprocal distribution costs are calculated using the limit and convergence of a transition probability matrix. And, a reciprocal distribution calculation is performed in a completely different way from the method of calculating reciprocal distribution known for the last several tens of years and in an effective manner, thereby calculation of reciprocal distribution costs at a high speed.
    Type: Application
    Filed: January 23, 2014
    Publication date: December 17, 2015
    Inventor: Yun HAN
  • Circuit board and electronic assembly
    Patent number: 9198286
    Abstract: A circuit board including a first patterned conductive layer and a second patterned conductive layer isolated from the first patterned conductive layer is provided. The first patterned conductive layer has first signal traces and first ground traces. The second patterned conductive layer has second signal traces and second ground traces. An orthogonal projection of the second ground trace on the first patterned conductive layer partially overlaps at least one of the first signal traces. An orthogonal projection of the first ground trace on the second patterned conductive layer partially overlaps at least one of the second signal traces. An electronic assembly including the afore-described circuit board and a chip package connected thereto is also provided.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: November 24, 2015
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Nai-Shung Chang, Yun-Han Chen, Chun-Yen Kang, Tsai-Sheng Chen
  • Substrate bias control circuit
    Patent number: 9158324
    Abstract: An integrated circuit includes a process voltage temperature (PVT) effect transducer responsive to a PVT effect, a PVT effect quantifier coupled to the PVT effect transducer and configured to quantify the PVT effect to provide an output, and a bias controller configured to receive the output of the PVT effect quantifier and provide a bias voltage for a substrate of an NMOS or a PMOS transistor. The bias controller is configured to compare the output received from the PVT effect quantifier to a threshold value, and decrease or increase the bias voltage depending on whether the output is higher or lower than the threshold value.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: October 13, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shyh-An Chi, Shiue Tsong Shen, Jyy Anne Lee, Yun-Han Lee
  • Networking Packages Based on Interposers
    Publication number: 20150289376
    Abstract: A package structure includes a networking unit including a plurality of switches/routers and a plurality of network interface units coupled to the plurality of switches/routers, and an interposer including a plurality of metal connections. The interposer is substantially free from functional elements built therein. A functional element is outside of, and bonded onto, the interposer, wherein the functional element is electrically coupled to the networking unit through the plurality of metal connections.
    Type: Application
    Filed: June 22, 2015
    Publication date: October 8, 2015
    Inventors: Yun-Han Lee, Mark Shane Peng, Shyh-An Chi
  • Memory error correction
    Patent number: 9135099
    Abstract: A method includes, by a first circuit, converting a plurality of bits in a first format to a second format. The plurality of bits in the second format is used, by a second circuit, to program a plurality of memory cells corresponding to the plurality of bits. The first format is a parallel format. The second format is a serial format. The first circuit and the second circuit are electrically coupled together in a chip. In some embodiments, the plurality of bits includes address information, cell data information, and program information of a memory cell that has an error. In some embodiments, the plurality of bits includes word data information of a word and error code and correction information corresponding to the word data information of the word.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: September 15, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Han Chen, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
  • System and Method for Designing Cell Rows
    Publication number: 20150213183
    Abstract: A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row.
    Type: Application
    Filed: April 6, 2015
    Publication date: July 30, 2015
    Inventors: Yun-Han Lee, Wu-An Kuo
  • COMMON TEMPLATE FOR ELECTRONIC ARTICLE
    Publication number: 20150213182
    Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.
    Type: Application
    Filed: April 6, 2015
    Publication date: July 30, 2015
    Inventors: William Wu Shen, Yun-Han Lee, Chin-Chou Liu, Hsien-Hsin Lee, Chung-Sheng Yuan, Chao-Yang Yeh, Wei-Cheng Wu, Ching-Fang Chen
  • METHOD AND APPARATUS FOR STORING WAVEFORM DATA
    Publication number: 20150193453
    Abstract: A method and apparatus for storing waveform data are disclosed. The apparatus for storing waveform data includes a channel information reception unit, a folder generation unit, a file generation unit, and an analysis information control unit. The channel information reception unit receives waveform data from an external measuring device. The folder generation unit generates a high level folder for each waveform measurement unit of the waveform data, and generates low level folders, in which information of each channel is stored, for the generated corresponding high level folder. The file generation unit generates waveform data files to be stored in the low level folders. The analysis information control unit stores a text file, corresponding to analysis information necessary for subchannel analysis, in the high level folder.
    Type: Application
    Filed: August 27, 2014
    Publication date: July 9, 2015
    Inventors: Yongdae KIM, Sang-Yun HAN, Jong Tai LEE, Haeng Seok KO, Sangwoo PARK
  • CIRCUIT BOARD AND ELECTRONIC ASSEMBLY
    Publication number: 20150195906
    Abstract: A circuit board including a first patterned conductive layer and a second patterned conductive layer isolated from the first patterned conductive layer is provided. The first patterned conductive layer has first signal traces and first ground traces. The second patterned conductive layer has second signal traces and second ground traces. An orthogonal projection of the second ground trace on the first patterned conductive layer partially overlaps at least one of the first signal traces. An orthogonal projection of the first ground trace on the second patterned conductive layer partially overlaps at least one of the second signal traces. An electronic assembly including the afore-described circuit board and a chip package connected thereto is also provided.
    Type: Application
    Filed: August 29, 2014
    Publication date: July 9, 2015
    Inventors: Nai-Shung CHANG, Yun-Han CHEN, Chun-Yen KANG, Tsai-Sheng CHEN
  • TRANSFORMER AND ADAPTER
    Publication number: 20150179333
    Abstract: A transformer including: a primary coil part including a multilayer substrate in which a plurality of substrates having coil patterns are stacked; a secondary coil part having the number of coil turns different from that of the primary coil part, positioned on at least one of upper and lower surfaces of the multilayer substrate, and including a conductor wire and an insulating material coating the conductor wire; and a shielding part disposed on the primary coil part and including at least one substrate on which a shielding pattern is provided
    Type: Application
    Filed: February 4, 2015
    Publication date: June 25, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Nak Jun JEONG, Jong Woo Kim, Sung Yun Han, Heung Gyoon Choi, Seung Hwan Lee, Young Seung Noh, Geun Young Park
  • TRANSFORMER AND ADAPTER
    Publication number: 20150179334
    Abstract: A transformer may include: a primary coil part including a plurality of substrates on which coil patterns are formed; a secondary coil part including an insulated coil; and a shielding part formed on the primary coil part and including one or more substrates on which a shielding pattern is formed.
    Type: Application
    Filed: May 28, 2014
    Publication date: June 25, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Nak Jun JEONG, Jong Woo Kim, Sung Yun Han, Heung Gyoon Choi, Seung Hwan Lee, Young Seung Noh, Geun Young Park