Patents by Inventor Yun Han

Yun Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8456434
    Abstract: Provided are a touch sensor and a method of operating the same. The touch sensor includes: a pulse signal generator for generating a pulse signal of which pulse width is calibrated in response to a control code; a pulse signal transmitter for transmitting the pulse signal when a touch object is out of contact with a touch pad and stopping transmitting the pulse signal when the touch object is in contact with the touch pad; a pulse signal detector for detecting the pulse signal transmitted through the pulse signal transmitter; and a controller recognizing a non-contact state and adjusting the control code to calibrate the pulse width of the pulse signal when the pulse signal detector detects the pulse signal. In the above-described configuration, the contact of the touch object with the touch pad can be sensed more precisely, and the occurrence of a malfunction in the touch sensor due to changed operating conditions can be prevented. As a result, the operating reliability of the touch sensor can be enhanced.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: June 4, 2013
    Assignee: Atlab Inc.
    Inventors: Byung-Joon Moon, Sang-Yun Han, Jae-Surk Hong, Duck-Young Jung
  • Patent number: 8434032
    Abstract: The present application discloses a method of generating an intellectual property (IP) block design kit including an IP block circuit design and a system-level characteristics table for manufacturing an integrated circuit. According at least one embodiment, the IP block circuit design is generated. The IP block circuit design is simulated based on predetermined configuration sets, and each configuration set has manufacturing options and/or operating conditions. A plurality of system-level models for the predetermined configuration sets are generated based on the simulation of the IP block circuit design. The system-level characteristics table is generated by arranging the predetermined configuration sets and the system-level models in compliance with a system-level characteristics table template of a system-level characteristics modeling device. Then the IP block circuit design and the system-level characteristics table are stored as the IP block design kit.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: April 30, 2013
    Assignee: Taiwan Semiconductor Maufacturing Company, Ltd.
    Inventors: Lee-Chung Lu, Yun-Han Lee, Wei-Li Chen, Tan-Li Chou, Kheng-Guan Tan, Shi-Hung Wang
  • Patent number: 8420488
    Abstract: A high voltage device is provided. The high voltage device includes a gate on a substrate, two source/drain regions in the substrate beside the gate, and a composite gate dielectric layer that includes at least two stacked continuous layers, extending from one side to another side of the gate. Wherein, the at least two stacked continuous layers is a combination of at least one thermal oxide layer and at least one chemical vapor deposited layer.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: April 16, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Yun-Han Ma, Ming-Tsung Lee, Shih-Ming Liang, Hwi-Huang Chen
  • Publication number: 20130065939
    Abstract: The present invention provides therapeutic nucleic acids such as interfering RNA (e.g., siRNA) that target the expression of genes associated with tumorigenesis and/or cell transformation, lipid particles (e.g., nucleic acid-lipid particles) comprising one or more (e.g., a cocktail) of the therapeutic nucleic acids, methods of making the lipid particles, and methods of delivering and/or administering the lipid particles, e.g., for the treatment of a cell proliferative disorder such as cancer.
    Type: Application
    Filed: September 23, 2010
    Publication date: March 14, 2013
    Applicants: Protiva Biotherapeutics, Inc., Department of Health and Human Services
    Inventors: Adam Judge, Yun-Han Lee, Ian MacLachlan, Snorri S. Thorgeirsson
  • Publication number: 20130015872
    Abstract: A probe card includes a plurality of probe pins, and a switch network connected to the plurality of probe pins. The switch network is configured to connect the plurality of probe pins in a first pattern, and reconnect the plurality of probe pins in a second pattern different from the first pattern.
    Type: Application
    Filed: July 15, 2011
    Publication date: January 17, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Han Lee, Mill-Jer Wang, Tan-Li Chou
  • Publication number: 20130009919
    Abstract: Provided is a display panel including: a display area; and a gate driver to receive a first clock signal, a first clock bar signal, a second clock signal and a second clock bar signal, the gate driver comprising a first stage and a second stage to respectively apply a first gate voltage and a second gate voltage to the display area, wherein the first clock signal and the first clock bar signal have opposite phases to each other, the second clock signal and the second clock bar signal have opposite phases to each other, the second clock bar signal has phases later than the first clock bar signal, the first stage discharges the first gate voltage based on the first clock signal and a first transfer signal, and the second stage outputs the first transfer signal based on the second clock bar signal.
    Type: Application
    Filed: December 7, 2011
    Publication date: January 10, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soo-Young PARK, In-Soo WANG, Gi-Chang LEE, Tae-Hyun KIM, Jeong-Yun HAN
  • Publication number: 20120273782
    Abstract: An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer.
    Type: Application
    Filed: May 27, 2011
    Publication date: November 1, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sandeep Kumar GOEL, Mill-Jer WANG, Chung-Sheng YUAN, Tom CHEN, Chao-Yang YEH, Chin-Chou LIU, Yun-Han LEE
  • Patent number: 8276110
    Abstract: A method of designing an integrated circuit includes providing an integrated circuit design including a power network. A voltage drop mitigation system is provided, which includes a power strap enhancer configured to automatically find a source node and a terminal node in the power network. A redundant strap for the power network using the voltage drop mitigation system is added, wherein the redundant strap interconnects the source node and the terminal node. After the step of adding the redundant strap, dummy patterns may be added.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: September 25, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dinesh Baviskar, Wen-Hao Chen, Chung-Sheng Yuan, Mark Shane Peng, Yun-Han Lee
  • Publication number: 20120238632
    Abstract: Described herein are methods and compositions for the detection of transthyretin (TTR), retinol binding protein (RBP) and retinol complex formation. The methods and compositions described herein also provide for the screening of modulators of retinol-RBP-TTR complex formation. Furthermore, the methods and compositions provide for therapeutic agents for the treatment and/or prevention of age-related macular degeneration and/or dystrophies.
    Type: Application
    Filed: September 13, 2011
    Publication date: September 20, 2012
    Applicant: ReVision Therapeutics, Inc.
    Inventors: Nathan L. Mata, Yun Han, Kenneth Widder, Jay Lichter
  • Patent number: 8242826
    Abstract: A master-slave retention flip-flop includes a master latch adapted to latch an input data signal and to output a latched master latch data signal based on an input clock signal, a slave latch coupled to an output of the master latch and adapted to output a latched slave latch data signal based on the input clock signal, and a retention latch embedded within one of the master and slave latches adapted to preserve data in a power down mode based on a power down control signal.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: August 14, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shyh-An Chi, Shiue Tsong Shen, Jyy Anne Lee, Yun-Han Lee
  • Patent number: 8227443
    Abstract: The present invention provides compositions comprising nucleic acids that target CSN5 gene expression and methods of using such compositions to silence CSN5 gene expression. More particularly, the present invention provides unmodified and chemically modified interfering RNA molecules which silence CSN5 gene expression and methods of use thereof, e.g., for treating cell proliferative disorders such as cancer. The present invention also provides nucleic acid-lipid particles that target CSN5 gene expression comprising an interfering RNA molecule, a cationic lipid, a non-cationic lipid, and optionally a conjugated lipid that inhibits aggregation of particles.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: July 24, 2012
    Assignees: Protiva Biotherapeutics, Inc., The United States of America, as represented by the Secretary, Department of Health and Human Services
    Inventors: Ian MacLachlan, Adam Judge, Snorri S. Thorgeirsson, Yun-Han Lee
  • Publication number: 20120147567
    Abstract: A package structure includes a networking unit including a plurality of switches/routers and a plurality of network interface units coupled to the plurality of switches/routers, and an interposer including a plurality of metal connections. The interposer is substantially free from functional elements built therein. A functional element is outside of, and bonded onto, the interposer, wherein the functional element is electrically coupled to the networking unit through the plurality of metal connections.
    Type: Application
    Filed: December 9, 2010
    Publication date: June 14, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Han Lee, Mark Shane Peng, Shyh-An Chi
  • Publication number: 20120131523
    Abstract: The present application discloses a method of generating an intellectual property (IP) block design kit including an IP block circuit design and a system-level characteristics table for manufacturing an integrated circuit. According at least one embodiment, the IP block circuit design is generated. The IP block circuit design is simulated based on predetermined configuration sets, and each configuration set has manufacturing options and/or operating conditions. A plurality of system-level models for the predetermined configuration sets are generated based on the simulation of the IP block circuit design. The system-level characteristics table is generated by arranging the predetermined configuration sets and the system-level models in compliance with a system-level characteristics table template of a system-level characteristics modeling device. Then the IP block circuit design and the system-level characteristics table are stored as the IP block design kit.
    Type: Application
    Filed: November 19, 2010
    Publication date: May 24, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lee-Chung LU, Yun-Han LEE, Wei-Li CHEN, Tan-Li CHOU, Kheng-Guan TAN, Shi-Hung WANG
  • Publication number: 20120112352
    Abstract: An integrated circuit system having an interposer and an integrated circuit with first and second bond pads, the integrated circuit die bonded to the interposer using the first bond pads. The integrated circuit having circuit blocks, that operate at different operating voltages and voltage regulator modules die bonded to the second bond pads of the integrated circuit. The voltage regulator modules converting a power supply voltage to the operating voltage of a respective circuit block and supply the respective operating voltage to the circuit block via the second bond pads.
    Type: Application
    Filed: November 10, 2010
    Publication date: May 10, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shyh-An CHI, Mark Shane PENG, Yun-Han LEE
  • Publication number: 20120043958
    Abstract: An electronic protection module adapted for an electronic device to protection information read and stored in a signal reading element. The electronic protection module includes a circuit board, a first loop, a cover, a first flexible circuit board with a second loop, a second flexible circuit board with a third loop, electrical conductor(s) and conductive element(s). When one of the first loop, second loop and the third loop is disconnected, the signal reading element will be disconnected and lose the information, thereby preventing information leak from the electronic device. The electronic device may be a card reader capable of reading a barcode type, magnetic strip type or chip type of a financial card, credit card or personal identity card.
    Type: Application
    Filed: February 1, 2011
    Publication date: February 23, 2012
    Inventors: Yu-Tsung CHEN, Yun-Han Chang, Jason Hsieh, Chien Hung Kuo
  • Patent number: 8113412
    Abstract: A method includes electrically grounding a first plurality of metal bumps on a first surface of an interconnection component to a common ground plate. A voltage contrast (VC) image of a second plurality of metal bumps of the interconnection component is generated. Grey levels of the second plurality of metal bumps in the VC image are analyzed to find defect connections between the second plurality of metal bumps and respective ones of the first plurality of metal bumps.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: February 14, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Nan-Hsin Tseng, Yun-Han Lee, Chin-Chou Liu, Ji-Jan Chen, Wei-Pin Changchien, Chien-Hui Chen
  • Publication number: 20110248759
    Abstract: A master-slave retention flip-flop includes a master latch adapted to latch an input data signal and to output a latched master latch data signal based on an input clock signal, a slave latch coupled to an output of the master latch and adapted to output a latched slave latch data signal based on the input clock signal, and a retention latch embedded within one of the master and slave latches adapted to preserve data in a power down mode based on a power down control signal.
    Type: Application
    Filed: April 12, 2010
    Publication date: October 13, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shyh-An CHI, Shiue Tsong SHEN, Jyy Anne LEE, Yun-Han LEE
  • Publication number: 20110185331
    Abstract: A method of designing an integrated circuit includes providing an integrated circuit design including a power network. A voltage drop mitigation system is provided, which includes a power strap enhancer configured to automatically find a source node and a terminal node in the power network. A redundant strap for the power network using the voltage drop mitigation system is added, wherein the redundant strap interconnects the source node and the terminal node. After the step of adding the redundant strap, dummy patterns may be added.
    Type: Application
    Filed: January 22, 2010
    Publication date: July 28, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dinesh Baviskar, Wen-Hao Chen, Chung-Sheng Yuan, Mark Shane Peng, Yun-Han Lee
  • Publication number: 20110178155
    Abstract: The present invention provides compositions comprising nucleic acids that target CSN5 gene expression and methods of using such compositions to silence CSN5 gene expression. More particularly, the present invention provides unmodified and chemically modified interfering RNA molecules which silence CSN5 gene expression and methods of use thereof, e.g., for treating cell proliferative disorders such as cancer. The present invention also provides nucleic acid-lipid particles that target CSN5 gene expression comprising an interfering RNA molecule, a cationic lipid, a non-cationic lipid, and optionally a conjugated lipid that inhibits aggregation of particles.
    Type: Application
    Filed: October 13, 2010
    Publication date: July 21, 2011
    Applicants: Protiva Biotherapeutics, Inc., The USA, as represented by the Secretary, Dept.of Health and Human Services
    Inventors: Ian MacLachlan, Adam Judge, Snorri S. Thorgeirsson, Yun-Han Lee
  • Publication number: 20110101217
    Abstract: Disclosed is a method for carrying out matrix-free mass spectrometry, which includes subjecting an analyte sample containing a self-assembled monolayer on the surface of a substrate to laser desorption/ionization. The method for carrying out matrix-free mass spectrometry involves simple pretreatment of an analyte sample with a cationic solution without using any solid matrix to cause effective laser desorption/ionization of the analyte sample, and minimizes a biochemical and physiological change in the sample that may occur during the pretreatment of the sample. In addition, the method is applicable to quantitative analysis because it provides high reproducibility of the results by virtue of the uniform treatment with the cationic solution over the whole areas of the sample. Further, the method enables two-dimensional mapping analysis.
    Type: Application
    Filed: April 24, 2009
    Publication date: May 5, 2011
    Applicant: KOREA RESEARCH INSTITUTE OF STANDARDS AND SCIENCE
    Inventors: Sang Yun Han, Tae Geol Lee, Dae Won Moon