Patents by Inventor Yun Hou

Yun Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit package and method
    Patent number: 11462418
    Abstract: A method includes attaching semiconductor devices to an interposer structure, attaching the interposer structure to a first carrier substrate, attaching integrated passive devices to the first carrier substrate, forming an encapsulant over the semiconductor devices and the integrated passive devices, debonding the first carrier substrate, attaching the encapsulant and the semiconductor devices to a second carrier substrate, forming a first redistribution structure on the encapsulant, the interposer structure, and the integrated passive devices, wherein the first redistribution structure contacts the interposer structure and the integrated passive devices, and forming external connectors on the first redistribution structure.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: October 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih Ting Lin, Szu-Wei Lu, Weiming Chris Chen, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
  • Optical transceiver and manufacturing method thereof
    Patent number: 11454773
    Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Sung-Hui Huang, Kuan-Yu Huang, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
  • Semiconductor structure and method of fabricating the same
    Patent number: 11450580
    Abstract: A semiconductor structure and a method for fabricating the same are disclosed. A semiconductor structure includes a first substrate, a package, a second substrate, and a lid. The package is attached to a first side of the first substrate. The second substrate is attached to a second side of the first substrate. The lid is connected to the first substrate and the second substrate. The lid includes a ring part over the first side of the first substrate. The ring part and the first substrate define a space and the package is accommodated in the space. The lid further includes a plurality of overhang parts which extend from corner sidewalls of the ring part toward the second substrate to cover corner sidewalls of the first substrate.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: September 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou, Chien-Yuan Huang
  • SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20220293508
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.
    Type: Application
    Filed: May 30, 2022
    Publication date: September 15, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Huang, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
  • Forming large chips through stitching
    Patent number: 11444038
    Abstract: A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Weiming Chris Chen
  • Chip package structure
    Patent number: 11437334
    Abstract: A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first bump and a first dummy bump between the chip and the substrate. The first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou
  • Method for forming a package structure for optical fiber
    Patent number: 11428879
    Abstract: A method for forming a package structure is provided. The method includes disposing an optical component and a waveguide over a substrate, forming a passivation layer over the substrate and covering the optical component and the waveguide, and forming a reflector including a metal layer and a first semiconductor layer on the passivation layer, wherein the metal layer and the first semiconductor layer are in contact with the passivation layer.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: August 30, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Hui Huang, Jui-Hsieh Lai, Shang-Yun Hou
  • PACKAGE STRUCTURE WITH UNDERFILL
    Publication number: 20220270894
    Abstract: A package structure is provided. The package structure includes a semiconductor die structure over a substrate and bonding structures between the semiconductor die and the substrate. The package structure also includes multiple solder elements over the substrate. The solder elements together surround the semiconductor die structure, and each of the solder elements is longer than a side of the semiconductor die structure. The package structure further includes an underfill material surrounding the bonding structures. The underfill material is substantially confined within a region surrounded by the solder elements. The underfill material is in direct contact with at least one of the solder elements.
    Type: Application
    Filed: May 5, 2022
    Publication date: August 25, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Yu HUANG, Sung-Hui HUANG, Jui-Hsieh LAI, Shang-Yun HOU
  • Package structure and method of fabricating the same
    Patent number: 11424219
    Abstract: A package structure includes a circuit substrate and a semiconductor device. The semiconductor device is disposed on and electrically connected to the circuit substrate. The semiconductor device includes an interconnection structure, a semiconductor die, an insulating encapsulant, a protection layer and electrical connectors. The interconnection structure has a first surface and a second surface. The semiconductor die is disposed on the first surface and electrically connected to the interconnection structure. The insulating encapsulant is encapsulating the semiconductor die and partially covering sidewalls of the interconnection structure. The protection layer is disposed on the second surface of the interconnection structure and partially covering the sidewalls of the interconnection structure, wherein the protection layer is in contact with the insulating encapsulant.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Wei Shen, Sung-Hui Huang, Shang-Yun Hou
  • CHIPLET INTERPOSER
    Publication number: 20220262742
    Abstract: Embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. The interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures.
    Type: Application
    Filed: June 4, 2021
    Publication date: August 18, 2022
    Inventors: Shang-Yun Hou, Weiming Chris Chen, Kuo-Chiang Ting, Hsien-Pin Hu, Wen-Chih Chiou, Chen-Hua Yu
  • Optical bench, method of making and method of using
    Patent number: 11415762
    Abstract: A method of forming an optical bench includes forming a reflector layer over a sloping side of a substrate. The method includes depositing a redistribution layer over the substrate. The method includes disposing an under bump metallization (UBM) layer over the redistribution layer. The method includes forming a passivation layer over the redistribution layer and surrounding sidewalls of the UBM layer. The method includes mounting a first optical component over an uppermost portion of the substrate, wherein the reflector layer is configured to reflect an electromagnetic wave from the first optical component, and the first optical component is mounted outside the trench.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ying-Hao Kuo, Shang-Yun Hou, Wan-Yu Lee
  • Package structures and methods of forming the same
    Patent number: 11417580
    Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Wen-Hsin Wei, Chi-Hsi Wu, Shang-Yun Hou, Jing-Cheng Lin, Hsien-Pin Hu, Ying-Ching Shih, Szu-Wei Lu
  • PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF
    Publication number: 20220254736
    Abstract: A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die.
    Type: Application
    Filed: March 3, 2022
    Publication date: August 11, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou
  • Semiconductor device and method of forming the same
    Patent number: 11410968
    Abstract: A semiconductor device includes a first Chip-On-Wafer (CoW) device having a first interposer and a first die attached to a first side of the first interposer; a second CoW device having a second interposer and a second die attached to a first side of the second interposer, the second interposer being laterally spaced apart from the first interposer; and a redistribution structure extending along a second side of the first interposer opposing the first side of the first interposer and extending along a second side of the second interposer opposing the first side of the second interposer, the redistribution structure extending continuously from the first CoW device to the second CoW device.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Shang-Yun Hou
  • Stacked Integrated Circuit Structure and Method of Forming
    Publication number: 20220246581
    Abstract: A semiconductor device and a method of forming the device are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material.
    Type: Application
    Filed: April 21, 2022
    Publication date: August 4, 2022
    Inventors: Wei-Ming Chen, Hsien-Pin Hu, Shang-Yun Hou, Wen-Hsin Wei
  • Chip-on-wafer structure with chiplet interposer
    Patent number: 11380611
    Abstract: A method of forming a semiconductor structure includes bonding a first die and a second die to a first side of a first interposer and to a first side of a second interposer, respectively, where the first interposer is laterally adjacent to the second interposer; encapsulating the first interposer and the second interposer with a first molding material; forming a first recess in a second side of the first interposer opposing the first side of the first interposer; forming a second recess in a second side of the second interposer opposing the first side of the second interposer; and filling the first recess and the second recess with a first dielectric material.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: July 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weiming Chris Chen, Kuo-Chiang Ting, Shang-Yun Hou
  • Semiconductor package and manufacturing method thereof
    Patent number: 11373946
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Huang, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
  • Structure and formation method of package structure with underfill
    Patent number: 11328936
    Abstract: A structure and a formation method of a package structure are provided. The method includes forming one or more solder elements over a substrate. The one or more solder elements surround a region of the substrate. The method also includes disposing a semiconductor die structure over the region of the substrate. The method further includes dispensing a polymer-containing liquid onto the region of the substrate. The one or more solder elements confine the polymer-containing liquid to being substantially inside the region. In addition, the method includes curing the polymer-containing liquid to form an underfill material.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Jui-Hsieh Lai, Shang-Yun Hou
  • Method of processing a received channel signal in a device to device communications link using multiple reference signals
    Patent number: 11323986
    Abstract: Described is a method of decoding a physical sidelink control channel (PSCCH). The method comprises: for a PSCCH candidate in a resource grid, processing a received demodulation reference signal (DMRS) in a subframe of the resource grid associated with the PSCCH candidate to determine one or more potential PSCCHs for decoding, each of the one or more potential PSCCHs being identified by resource block (RB) position in the resource grid and a corresponding DMRS cyclic shift (ncs) value. This step is repeated for at least one other DMRS in the subframe to determine one or more potential PSCCHs for the at least one other DMRS. Then, a subset L of PSCCHs is selected from the potential PSCCHs. The selected subset L of PSCCHs together with their corresponding DMRS cyclic shift (ncs) values are made available for use in a decoding process for the received channel signal.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: May 3, 2022
    Assignee: Hong Kong Applied Science and Technology Research Institue Company Limited
    Inventors: Eddy Chiu, Yun Hou, Yuyi Mao, Xiangyu Liu, Ching Hong Chris Leung, Man Wai Victor Kwan, Kong Chau Eric Tsang
  • PHOTONIC PACKAGE AND METHOD OF MANUFACTURE
    Publication number: 20220099887
    Abstract: A package includes silicon waveguides on a first side of an oxide layer; photonic devices on the first side of the oxide layer, wherein the photonic devices are coupled to the silicon waveguides; redistribution structures over the first side of the oxide layer, wherein the redistribution structures are electrically connected to the photonic devices; a hybrid interconnect structure on a second side of the oxide layer, wherein the hybrid interconnect structure includes a stack of silicon nitride waveguides that are separated by dielectric layers; and through vias extending through the hybrid interconnect structure and the oxide layer, wherein the through vias make physical and electrical connection to the redistribution structures.
    Type: Application
    Filed: June 7, 2021
    Publication date: March 31, 2022
    Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Kuo-Chiang Ting, Jiun Yi Wu, Hung-Yi Kuo, Shang-Yun Hou