Patents by Inventor Yun Hou

Yun Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20210118844
    Abstract: A semiconductor device includes a first Chip-On-Wafer (CoW) device having a first interposer and a first die attached to a first side of the first interposer; a second CoW device having a second interposer and a second die attached to a first side of the second interposer, the second interposer being laterally spaced apart from the first interposer; and a redistribution structure extending along a second side of the first interposer opposing the first side of the first interposer and extending along a second side of the second interposer opposing the first side of the second interposer, the redistribution structure extending continuously from the first CoW device to the second CoW device.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 22, 2021
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Shang-Yun Hou
  • Stacked integrated circuit structure and method of forming
    Patent number: 10985137
    Abstract: A semiconductor device, and a method of forming the device, are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ming Chen, Hsien-Pin Hu, Shang-Yun Hou, Wen Hsin Wei
  • Chip package structure
    Patent number: 10985125
    Abstract: A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shu-Chia Hsu, Leu-Jen Chen, Yi-Wei Liu, Shang-Yun Hou, Jui-Hsieh Lai, Tsung-Yu Chen, Chien-Yuan Huang, Yu-Wei Chen
  • Conductive vias in semiconductor packages and methods of forming same
    Patent number: 10978346
    Abstract: An embodiment method includes bonding a first die to a first side of an interposer, the interposer comprising a substrate; after bonding the first die to the first side of the interposer, depositing a first insulating layer on a second side of the interposer opposite the first side; patterning an opening through the substrate and the first insulating layer; and depositing a second insulating layer over the first insulating layer and along sidewalls and a lateral surface of the opening. The second insulating layer comprises silicon. The method further includes removing lateral portions of the second insulating layer to define a sidewall spacer on sidewalls of the opening and forming a through via in the opening, wherein the through via is electrically connected to the first die.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Hui Huang, Hung-Pin Chang, Sao-Ling Chiu, Shang-Yun Hou, Wan-Yu Lee
  • Interconnect Chips
    Publication number: 20210098408
    Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Kuo-Chiang Ting, Chi-Hsi Wu, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Ting-Yu Yeh
  • Stacked integrated circuit structure and method of forming
    Patent number: 10964667
    Abstract: A semiconductor device, and a method of forming the device, are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ming Chen, Hsien-Pin Hu, Shang-Yun Hou, Wen-Hsin Wei
  • PHOTONIC SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
    Publication number: 20210088723
    Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.
    Type: Application
    Filed: July 16, 2020
    Publication date: March 25, 2021
    Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Kuo-Chiang Ting, Sung-Hui Huang, Shang-Yun Hou, Chi-Hsi Wu
  • OPTICAL BENCH, METHOD OF MAKING AND METHOD OF USING
    Publication number: 20210088737
    Abstract: A method of forming an optical bench includes forming a reflector layer over a sloping side of a substrate. The method includes depositing a redistribution layer over the substrate. The method includes disposing an under bump metallization (UBM) layer over the redistribution layer. The method includes forming a passivation layer over the redistribution layer and surrounding sidewalls of the UBM layer. The method includes mounting a first optical component over an uppermost portion of the substrate, wherein the reflector layer is configured to reflect an electromagnetic wave from the first optical component, and the first optical component is mounted outside the trench.
    Type: Application
    Filed: December 9, 2020
    Publication date: March 25, 2021
    Inventors: Ying-Hao KUO, Shang-Yun HOU, Wan-Yu LEE
  • PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20210082894
    Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weiming Chris Chen, Chi-Hsi Wu, Chih-Wei Wu, Kuo-Chiang Ting, Szu-Wei Lu, Shang-Yun Hou, Ying-Ching Shih, Hsien-Ju Tsou, Cheng-Chieh Li
  • Package structure for optical fiber and method for forming the same
    Patent number: 10948668
    Abstract: A method for forming a package structure is provided, including: disposing an optical component and a waveguide over a first substrate; forming a passivation layer over the first substrate and covering the optical component and the waveguide; removing a portion of the passivation layer to form a first opening; and disposing a reflector over the passivation layer, wherein a metal layer of the reflector is formed in the first opening.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sung-Hui Huang, Jui-Hsieh Lai, Shang-Yun Hou
  • Method of Processing a Received Channel Signal in a Device to Device Communications Link
    Publication number: 20210076433
    Abstract: Described is a method of decoding a physical sidelink shared channel (PSSCH) involving physical sidelink control channel (PSCCH) resource grid search space reduction, timing offset (TO) estimation, and reference symbol identification. Resource grid search space reduction may include identifying resource blocks (RBs) having a signal power below a first threshold such that said RBs can be excluded from further processing. Search space reduction may additionally or alternatively include identifying RB pairs where a difference in signal power between the RBs comprising each pair of RBs is above a second threshold and excluding any such said RB pairs from further processing. TO compensation may include circularly correlating TO-compensated received DMRSs and their corresponding local DMRSs to obtain energy or power profiles.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 11, 2021
    Inventors: Yun Hou, Yuyi Mao, Eddy Chiu, Xiangyu Liu, Yaming Luo, Man Wai Kwan, Kong Chau Eric Tsang
  • CHIP PACKAGE STRUCTURE
    Publication number: 20210066230
    Abstract: A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first bump and a first dummy bump between the chip and the substrate. The first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu HUANG, Sung-Hui HUANG, Shang-Yun HOU
  • Semiconductor Devices and Methods of Manufacture
    Publication number: 20210043571
    Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.
    Type: Application
    Filed: May 29, 2020
    Publication date: February 11, 2021
    Inventors: Shang-Yun Hou, Hsien-Pin Hu
  • Photonic Semiconductor Device and Method
    Publication number: 20210018678
    Abstract: A method includes forming silicon waveguide sections in a first oxide layer over a substrate, the first oxide layer disposed on the substrate, forming a routing structure over the first oxide layer, the routing structure including one or more insulating layers and one or more conductive features in the one or more insulating layers, recessing regions of the routing structure, forming nitride waveguide sections in the recessed regions of the routing structure, wherein the nitride waveguide sections extend over the silicon waveguide sections, forming a second oxide layer over the nitride waveguide sections, and attaching semiconductor dies to the routing structure, the dies electrically connected to the conductive features.
    Type: Application
    Filed: August 17, 2020
    Publication date: January 21, 2021
    Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Kuo-Chiang Ting, Pin-Tso Lin, Sung-Hui Huang, Shang-Yun Hou, Chi-Hsi Wu
  • CHIP PACKAGE STRUCTURE
    Publication number: 20210005567
    Abstract: A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.
    Type: Application
    Filed: September 23, 2020
    Publication date: January 7, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu HUANG, Sung-Hui HUANG, Shu-Chia HSU, Leu-Jen CHEN, Yi-Wei LIU, Shang-Yun HOU, Jui-Hsieh LAI, Tsung-Yu CHEN, Chien-Yuan HUANG, Yu-Wei CHEN
  • Package structure and method for forming the same
    Patent number: 10886147
    Abstract: A method for forming the package structure is provided. The method includes forming a die structure over a first surface of a first substrate, and forming a plurality of electrical connectors below a second surface of the first substrate. The method also includes forming a first protruding structure below the second surface of the first substrate, and the electrical connectors are surrounded by the first protruding structure. The method further includes forming a second protruding structure over a second substrate, and bonding the first substrate to the second substrate. The electrical connectors are surrounded by the second protruding structure, and the first protruding structure does not overlap with the second protruding structure.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: January 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou
  • Package Structures and Methods of Forming the Same
    Publication number: 20200402877
    Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Inventors: Chen-Hua Yu, Wen-Hsin Wei, Chi-Hsi Wu, Shang-Yun Hou, Jing-Cheng Lin, Hsien-Pin Hu, Ying-Ching Shih, Szu-Wei Lu
  • Chip package structure with dummy bump and method for forming the same
    Patent number: 10872871
    Abstract: A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a dummy bump over a second surface of the first substrate. The first surface is opposite the second surface, and the dummy bump is electrically insulated from the chip. The method includes cutting through the first substrate and the dummy bump to form a cut substrate and a cut dummy bump. The cut dummy bump is over a corner portion of the cut substrate, a first sidewall of the cut dummy bump is substantially coplanar with a second sidewall of the cut substrate, and a third sidewall of the cut dummy bump is substantially coplanar with a fourth sidewall of the cut substrate.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sung-Hui Huang, Kuan-Yu Huang, Shang-Yun Hou, Yushun Lin, Heh-Chang Huang, Shu-Chia Hsu, Pai-Yuan Li, Kung-Chen Yeh
  • Interconnect chips
    Patent number: 10867954
    Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chiang Ting, Chi-Hsi Wu, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Ting-Yu Yeh
  • Optical transceiver and manufacturing method thereof
    Patent number: 10866373
    Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Sung-Hui Huang, Kuan-Yu Huang, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu