Abstract: An internal voltage generation circuit includes a comparison signal generation unit configured to compare an internal voltage with first and second reference voltages and generate first and second comparison signals; a transfer unit configured to transfer the first comparison signal as a pull-up signal in response to the second comparison signal, transfer the second comparison signal as a pull-down signal in response to the first comparison signal, transfer a power supply voltage as the pull-up signal when the second comparison signal is enabled and transfer a ground voltage as the pull-down signal when the first comparison signal is enabled; and a driving unit configured to drive a node in response to the pull-up signal and the pull-down signal and generate the internal voltage.

Abstract: A self refresh circuit includes a continuous output interrupting unit and a glitch removing unit. The continuous output interrupting unit is configured to receive a delay self refresh signal, transmit a pulse of an internal active signal as a first output active signal and interrupt the transmission of the pulse of the internal active signal during a first time period. The glitch removing unit is configured to generate and output a second output active signal when the first output active signal has a predetermined pulse width.

Abstract: A test device of a semiconductor integrated circuit includes: an oscillation unit including a plurality of oscillation circuits and configured to activate the respective oscillation circuits in response to a test mode signal and output a plurality of oscillation signals; a switching unit configured to extract only an activated signal among the plurality of oscillation signals; a frequency division unit configured to divide a signal outputted from the switching unit at a predetermined division ratio and generate a divided oscillation signal; and a data buffer unit configured to buffer the divided oscillation signal to output through a data pad.

Abstract: A power-up signal generation circuit of a semiconductor apparatus includes a driver configured to generate a power-up signal in response to a first voltage. The power-up signal generation circuit may also comprise a power control unit configured to provide the first voltage or a second voltage as a power supply voltage to the driver in response to the power-up signal.

Abstract: A digital temperature information generating apparatus for a semiconductor integrated circuit includes a temperature information generating block that, in response to a reset signal, latches and decodes multiple divided signals obtained by multiple-dividing a second control signal at a timing corresponding to a change in period of a first control signal according to a temperature, and generates temperature information, and pads through which the generated temperature information is output.

Abstract: A self refresh circuit includes a continuous output interrupting unit and a glitch removing unit. The continuous output interrupting unit is configured to receive a delay self refresh signal, transmit a pulse of an internal active signal as a first output active signal and interrupt the transmission of the pulse of the internal active signal during a first time period. The glitch removing unit is configured to generate and output a second output active signal when the first output active signal has a predetermined pulse width.

Abstract: Disclosed is a delay circuit. The delay circuit includes a pulse generating unit, a timing adjusting unit, and a pulse width adjusting unit. The pulse generating unit is configured to generate a pulse signal having a preset width in response to a rising edge of an input signal. The timing adjusting unit is configured to activate an output signal in response to the pulse signal after a predetermined time has lapsed. The pulse width adjusting unit is configured to adjust a pulse width of the output signal in response to the activation of the output signal.

Abstract: A test device of a semiconductor integrated circuit includes: an oscillation unit including a plurality of oscillation circuits and configured to activate the respective oscillation circuits in response to a test mode signal and output a plurality of oscillation signals; a switching unit configured to extract only an activated signal among the plurality of oscillation signals; a frequency division unit configured to divide a signal outputted from the switching unit at a predetermined division ratio and generate a divided oscillation signal; and a data buffer unit configured to buffer the divided oscillation signal to output through a data pad.

Abstract: A refresh period signal generator with a digital temperature information generation function includes a temperature information generating part configured to generate temperature information by using a first period signal and a second period signal, a refresh period signal generating part configured to output a refresh period signal by selecting one signal having a shorter period between the first period signal and the second period signal, and an operation timing control part operating the temperature information generating part and the refresh period signal generating part at a predetermined timing.

Abstract: A semiconductor memory apparatus includes a MOS transistor configured to be supplied with a first voltage through a bulk terminal thereof. The semiconductor memory apparatus also includes a current control unit configured to be connected to a source terminal of the MOS transistor, receive a power down mode enable signal and a self refresh mode enable signal, apply a second voltage to the source terminal during a power down mode or a self refresh mode, and apply the first voltage to the source terminal during modes other than the power down mode and the self refresh mode.

Abstract: Disclosed is a delay circuit. The delay circuit includes a pulse generating unit, a timing adjusting unit, and a pulse width adjusting unit. The pulse generating unit is configured to generate a pulse signal having a preset width in response to a rising edge of an input signal. The timing adjusting unit is configured to activate an output signal in response to the pulse signal after a predetermined time has lapsed. The pulse width adjusting unit is configured to adjust a pulse width of the output signal in response to the activation of the output signal.

Abstract: A semiconductor memory apparatus includes a MOS transistor configured to be supplied with a first voltage through a bulk terminal thereof. The semiconductor memory apparatus also includes a current control unit configured to be connected to a source terminal of the MOS transistor, receive a power down mode enable signal and a self refresh mode enable signal, apply a second voltage to the source terminal during a power down mode or a self refresh mode, and apply the first voltage to the source terminal during modes other than the power down mode and the self refresh mode.

Abstract: A period signal generator comprises a first period signal generating unit for generating a first period signal of which period changes according to a temperature, a second period signal generating unit for generating a second period signal which has a constant period regardless of a temperature, and a period signal output control unit for comparing the first period signal with the second period signal and selecting and outputting the first period signal in case that the period of the first period signal is shorter than that of the second period signal.

Abstract: A refresh period signal generator with a digital temperature information generation function includes a temperature information generating part configured to generate temperature information by using a first period signal and a second period signal, a refresh period signal generating part configured to output a refresh period signal by selecting one signal having a shorter period between the first period signal and the second period signal, and an operation timing control part operating the temperature information generating part and the refresh period signal generating part at a predetermined timing.

Abstract: A digital temperature information generating apparatus for a semiconductor integrated circuit includes a temperature information generating block that, in response to a reset signal, latches and decodes multiple divided signals obtained by multiple-dividing a second control signal at a timing corresponding to a change in period of a first control signal according to a temperature, and generates temperature information, and pads through which the generated temperature information is output.

Abstract: A period signal generator comprises a first period signal generating unit for generating a first period signal of which period changes according to a temperature, a second period signal generating unit for generating a second period signal which has a constant period regardless of a temperature, and a period signal output control unit for comparing the first period signal with the second period signal and selecting and outputting the first period signal in case that the period of the first period signal is shorter than that of the second period signal.

Abstract: A temperature compensated self-refresh circuit maintains a stable current characteristic by maintaining a predetermined self-refresh cycle to cope with a process skew and a voltage change in a low power consumption memory product and by changing the self-refresh cycle only depending on temperature change. The temperature compensated self-refresh circuit is provided with a reference voltage generating unit adapted and configured to use an internal power voltage of a Widlar type so as to reduce a process skew and to have NMOS transistors with a LVT (Low Voltage Transistor) structure so as to have the same voltage as that of a temperature sense unit, thereby maintaining a predetermined cycle of an oscillating signal coping with the process skew.

Abstract: Disclosed is a method for analyzing a defect of a semiconductor device, and more particularly a method for electrically analyzing a defect of a transistor formed in a cell having a latch structure, such as SRAM or a sense amplifier of DRAM. The defect analyzing method according to the present invention comprises the steps of forming a test SRAM cell array in a scribe lane region of a wafer which is formed with a plurality of SRAM chips, forming a pad portion for testing the SRAM cell array on the scribe lane region, and applying a predetermined test voltage to the SRAM cell array through the pad portion. The respective array cells constituting the SRAM cell array are provide with two word lines, and individual test voltages can be applied through the pad portion to the two word lines, respectively.

Abstract: A low power semiconductor memory device can reduce power consumption of the whole chip by activating a bit line sense amplifier and a sub word line driver for driving a selected memory cell array block. The low power semiconductor memory device comprises a plurality of memory cell array blocks, a plurality of sense amplifier arrays, a sub word line driver array and a block selecting activation control unit. The block selecting activation control unit selectively activates the sub word line driver and the sense amplifier for driving the memory cell array block corresponding to a block selecting address.

Abstract: A device for controlling a temperature compensated self-refresh period clamps a self-refresh signal at high temperature over a specific temperature to maintain the self-refresh period, thereby removing dependency on temperature. In the device, an oscillating signal having a period varied depending on temperature change is generated below a specific temperature, and a period of a first period signal is compared with that of the oscillating signal applied from a temperature compensated self-refresh circuit unit over the specific temperature. When the period of the oscillating signal is shorter than that of the first signal, a pulse width of an oscillating strobe signal generated in response to a plurality of division signals each obtained by dividing the period of the oscillating signal at a predetermined ratio is controlled, so that an oscillating period of the temperature compensated self-refresh circuit unit is kept at a fixed state.