Patents by Inventor Yun-seok Kim

Yun-seok Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7406020
    Abstract: A method of writing data on a storage device using a probe technique. In the method of writing data on a memory device including a resistive probe used for reading and writing of data, a ferroelectric writing medium on which data is written by the resistive probe, and a lower electrode disposed on a bottom surface of the ferroelectric writing medium, heat and an electric field are applied simultaneously to a domain of the ferroelectric writing medium, on which the data will be written, by applying a voltage to the resistive probe and the lower electrode.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: July 29, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-bum Hong, Sung-dong Kim, Ju-hwan Jung, Dong-ki Min, Hong-sik Park, Kyoung-lock Baeck, Chul-min Park, Yun-seok Kim
  • Patent number: 7396777
    Abstract: Methods of fabricating high-k dielectric layers having reduced impurities for use in semiconductor applications are disclosed. The methods include the steps of: forming a stacked dielectric layer having a first dielectric layer and a second dielectric layer formed on a semiconductor substrate using an ALD method, in combination with a post-treatment step performed to the stacked dielectric layer. The steps of forming the stacked dielectric layer and performing the post-treatment are repeated at least once, thereby fabricating the high-k dielectric layer.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: July 8, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung-Suk Jung, Jong-Ho Lee, Ha-Jin Lim, Jae-Eun Park, Yun-Seok Kim, Jong-Ho Yang
  • Publication number: 20070176242
    Abstract: A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.
    Type: Application
    Filed: March 21, 2007
    Publication date: August 2, 2007
    Inventors: Jong-Ho Lee, Ho-Kyu Kang, Yun-Seok Kim, Seok-Joo Doh, Hyung-Suk Jung
  • Publication number: 20070178637
    Abstract: A method of fabricating a gate of a semiconductor device using an oxygen-free ashing process is disclosed. The method includes forming a high-k dielectric film, having a dielectric constant higher than a silicon oxide film, on a semiconductor substrate including an NMOS region and a PMOS region, forming an etching target film on the high-k dielectric film, forming a photoresist pattern to expose any one region of the two regions, on the etching target film, etching the etching target film using the photoresist pattern as an etching mask, and removing the photoresist pattern using plasma formed in the presence of an oxygen-free reactive gas.
    Type: Application
    Filed: January 30, 2007
    Publication date: August 2, 2007
    Inventors: Hyung-suk Jung, Cheol-kyu Lee, Jong-ho Lee, Sung-kee Han, Yun-seok Kim
  • Publication number: 20070023842
    Abstract: A first transistor includes a first channel region of a first conductivity type located at a first surface region of a semiconductor substrate, a first gate dielectric which includes a first HfO2 layer located over the first channel region, and a first gate located over the first gate dielectric. The first gate includes a first polysilicon layer doped with an impurity of the first conductivity type. The second transistor includes a second channel region of a second conductivity type located at a second surface region of the semiconductor substrate, a second gate dielectric which includes a second HfO2 layer and an Al2O3 layer located over the second channel region, and a second gate located over the second gate dielectric. The second gate includes a second polysilicon layer doped with an impurity of the second conductivity type, and the second conductivity type is opposite the first conductivity type.
    Type: Application
    Filed: May 12, 2006
    Publication date: February 1, 2007
    Inventors: Hyung-suk Jung, Jong-ho Lee, Ha-jin Lim, Yun-seok Kim
  • Publication number: 20060263910
    Abstract: A data recording medium including a ferroelectric layer and a method of manufacturing the same are provided. In the data recording medium, a barrier layer, a conductive layer, and a seed layer are sequentially stacked on a substrate. A data recording layer is formed on the seed layer and has a vertical residual polarization.
    Type: Application
    Filed: February 17, 2006
    Publication date: November 23, 2006
    Inventors: Seung-bum Hong, Yun-seok Kim, Seung-hyun Kim, Kwang-soo No
  • Publication number: 20060257563
    Abstract: There are provided methods of fabricating a silicon-doped metal oxide layer on a semiconductor substrate using an atomic layer deposition technique. The methods include an operation of repeatedly performing a metal oxide layer formation cycle K times and an operation of repeatedly performing a silicon-doped metal oxide layer formation cycle Q times. At least one of the values K and Q is an integer of 2 or more. K and Q are integers ranging from 1 to about 10 respectively. The metal oxide layer formation cycle includes the steps of supplying a metal source gas to a reactor containing the substrate, and then injecting an oxide gas into the reactor. The silicon-doped metal oxide layer formation cycle includes supplying a metal source gas including silicon into a reactor containing the substrate, and then injecting an oxide gas into the reactor.
    Type: Application
    Filed: January 11, 2006
    Publication date: November 16, 2006
    Inventors: Seok-Joo Doh, Shi-Woo Rhee, Jong-Pyo Kim, Jung-Hyoung Lee, Jong-Ho Lee, Yun-Seok Kim
  • Publication number: 20060244147
    Abstract: In a method of manufacturing a dielectric structure, after a tunnel oxide layer pattern is formed on a substrate, a floating gate is formed on the tunnel oxide layer. After a first dielectric layer pattern including a metal silicon oxide and a second dielectric layer pattern including a metal silicon oxynitride are formed, a control gate is formed on the dielectric structure. Since the dielectric structure includes at least one metal silicon oxide layer and at least one metal silicon oxynitride layer, the dielectric structure may have a high dielectric constant and a good thermal resistance. A non-volatile semiconductor memory device including the dielectric structure may have good electrical characteristics such as a large capacitance and a low leakage current.
    Type: Application
    Filed: January 25, 2006
    Publication date: November 2, 2006
    Inventors: Jong-Cheol Lee, Sung-Tae Kim, Young-Sun Kim, Cha-Young Yoo, Gab-Jin Nam, Young-Geun Park, Jae-Hyoung Choi, Jae-Hyun Yeo, Ha-Jin Lim, Yun-Seok Kim
  • Publication number: 20060166476
    Abstract: In a method of manufacturing a dielectric structure, after a first dielectric layer is formed on a substrate by using a metal oxide doped with silicon, the substrate is placed on a susceptor of a chamber. By treating the first dielectric layer with a plasma in controlling a voltage difference between the susceptor and a ground, a second dielectric layer is formed on the first dielectric layer. The second dielectric layer including a metal oxynitride doped with silicon having enough content of nitrogen is formed on the first dielectric layer. Therefore, dielectric properties of the dielectric structure comprising the first and the second dielectric layers can be improved and a leakage current can be greatly decreased. By adapting the dielectric structure to a gate insulation layer and/or to a dielectric layer of a capacitor or of a non-volatile semiconductor memory device, capacitances and electrical properties can be improved.
    Type: Application
    Filed: January 25, 2006
    Publication date: July 27, 2006
    Inventors: Jong-Cheol Lee, Sung-Tae Kim, Young-Sun Kim, Cha-Young Yoo, Gab-Jin Nam, Young-Geun Park, Jae-Hyoung Choi, Jae-Hyun Yeo, Ha-Jin Lim, Yun-Seok Kim
  • Publication number: 20060115993
    Abstract: High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.
    Type: Application
    Filed: January 17, 2006
    Publication date: June 1, 2006
    Inventors: Seok-Joo Doh, Hyung-suk Jung, Nae-in Lee, Jong-ho Lee, Yun-seok Kim
  • Patent number: 7037863
    Abstract: High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: May 2, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Joo Doh, Hyung-suk Jung, Nae-in Lee, Jong-ho Lee, Yun-seok Kim
  • Publication number: 20050255246
    Abstract: There are provided methods of fabricating a metal silicate layer on a semiconductor substrate using an atomic layer deposition technique. The methods include performing a metal silicate layer formation cycle at least one time in order to form a metal silicate layer having a desired thickness. The metal silicate layer formation cycle includes an operation of repeatedly performing a metal oxide layer formation cycle K times and an operation of repeatedly performing a silicon oxide layer formation cycle Q times. K and Q are integers ranging from 1 to 10 respectively. The metal oxide layer formation cycle includes the steps of supplying a metal source gas to a reactor containing the substrate, exhausting the metal source gas remaining in a reactor to clean the inside of the reactor, and then supplying an oxide gas into the reactor.
    Type: Application
    Filed: May 12, 2005
    Publication date: November 17, 2005
    Inventors: Yun-Seok Kim, Jong-Pyo Kim, Ha-Jin Lim, Jae-Eun Park, Hyung-Suk Jung, Jong-Ho Lee, Jong-Ho Yang
  • Publication number: 20050233598
    Abstract: Methods of fabricating high-k dielectric layers having reduced impurities for use in semiconductor applications are disclosed. The methods include the steps of: forming a stacked dielectric layer having a first dielectric layer and a second dielectric layer formed on a semiconductor substrate using an ALD method, in combination with a post-treatment step performed to the stacked dielectric layer. The steps of forming the stacked dielectric layer and performing the post-treatment are repeated at least once, thereby fabricating the high-k dielectric layer.
    Type: Application
    Filed: April 15, 2005
    Publication date: October 20, 2005
    Inventors: Hyung-Suk Jung, Jong-Ho Lee, Ha-Jin Lim, Jae-Eun Park, Yun-Seok Kim, Jong-Ho Yang
  • Publication number: 20050148127
    Abstract: A semiconductor device is disclosed comprising an improved gate dielectric layer formed of a high dielectric alloy-like composite together with a method for fabricating the same. The semiconductor device comprises a semiconductor substrate and a gate dielectric layer consisting essentially of a high-k alloy-like composite containing a first element, a second element, and oxygen (O). The first element is at least one member selected from a first group consisting of Al, La, Y, Ga, and In. The second element is at least one member selected from a second group consisting of Hf, Zr, and Ti. A diffusion barrier is formed on the gate dielectric layer, and a gate is formed on the diffusion barrier.
    Type: Application
    Filed: November 15, 2004
    Publication date: July 7, 2005
    Inventors: Hyung-Suk Jung, Jong-Ho Lee, Seok-Joo Doh, Yun-Seok Kim
  • Publication number: 20050147018
    Abstract: A recording medium including a ferroelectric layer, a nonvolatile memory device including the recording medium and methods of wiring and reading data in the memory device. The recording medium includes: a lower electrode; a ferroelectric layer to which data is recorded, formed on the lower electrode; a barrier layer formed on the ferroelectric layer; and a semiconductor layer formed on the barrier layer. The nonvolatile memory device includes a probe that reads and writes the data. Furthermore, in the method of writing data, a writing voltage is applied between the probe, which contacts the semiconductor layer, and the lower electrode and, in the method of reading data, a state of a remanent polarization of the ferroelectric layer is determined by applying a reading voltage between the probe and the semiconductor layer.
    Type: Application
    Filed: August 25, 2004
    Publication date: July 7, 2005
    Inventors: Yun-seok Kim, Seung-bum Hong, Kwang-soo No
  • Patent number: 6903302
    Abstract: A method for manufacturing valve seats using a laser cladding process is provided that includes forming a casting material on which the valve seats are to be formed; fabricating a valve seat target position on which laser cladding will be performed, the valve seat target position being provided at a location on the casting material where a valve seat is to be formed; removing an oxidation film formed on the valve seat target position; injecting a metal powder mixture on the valve seat target position, the metal powder mixture being realized through a mixture of two or more metal powders at a predetermined ratio by weight %; and irradiating a laser beam on the metal powder mixture to clad the metal powder mixture on the valve seat target position to thereby form the valve seat.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: June 7, 2005
    Assignee: Hyundai Motor Company
    Inventors: Yun-Seok Kim, Jea-Woong Yi, Jae-Hwan Kim, Phil-Gi Lee
  • Publication number: 20050098839
    Abstract: A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.
    Type: Application
    Filed: September 1, 2004
    Publication date: May 12, 2005
    Inventors: Jong-Ho Lee, Ho-Kyu Kang, Yun-Seok Kim, Seok-Joo Doh, Hyung-Suk Jung
  • Patent number: 6875678
    Abstract: High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: April 5, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung-suk Jung, Nae-in Lee, Jong-ho Lee, Yun-seok Kim
  • Publication number: 20050052984
    Abstract: A method of writing data on a storage device using a probe technique. In the method of writing data on a memory device including a resistive probe used for reading and writing of data, a ferroelectric writing medium on which data is written by the resistive probe, and a lower electrode disposed on a bottom surface of the ferroelectric writing medium, heat and an electric field are applied simultaneously to a domain of the ferroelectric writing medium, on which the data will be written, by applying a voltage to the resistive probe and the lower electrode.
    Type: Application
    Filed: September 7, 2004
    Publication date: March 10, 2005
    Inventors: Seung-bum Hong, Sung-dong Kim, Ju-hwan Jung, Dong-ki Min, Hong-sik Park, Kyoung-lock Baeck, Chul-min Park, Yun-seok Kim
  • Publication number: 20050037630
    Abstract: High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.
    Type: Application
    Filed: September 10, 2003
    Publication date: February 17, 2005
    Inventors: Seok-Joo Doh, Hyung-suk Jung, Nae-in Lee, Jong-ho Lee, Yun-seok Kim