Abstract: An image sensor module is provided. The image sensor module includes a printed circuit board (PCB), an image sensor chip disposed on a first plane of the PCB and electrically connected to the PCB, and an image signal processing chip disposed on the first plane of the PCB and electrically connected to the PCB. An aspect ratio of the image signal processing chip is at least two times greater than an aspect ratio of the image sensor chip. A minimum feature size of a metal line implemented in the image sensor chip is at least 1.5 times greater than a minimum feature size of a metal line implemented in the image signal processing chip.

Abstract: Provided is a liquid crystal display including: a first substrate; a gate line, a data line, and a common voltage line formed on the first substrate; a first passivation layer formed on the gate line, the data line, and the common voltage line; and a pixel electrode and a common electrode formed on the first passivation layer and overlapping each other with a second passivation layer therebetween, and the common electrode is connected to the common voltage line through a common contact hole, and the common contact hole is disposed for every two or more dots.

Abstract: A connection system of semiconductor packages includes: a printed circuit board; a first semiconductor package disposed on a first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; a second semiconductor package disposed on a second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures; and a third semiconductor package disposed on the first semiconductor package and connected to the first semiconductor package through third electrical connection structures. The first semiconductor package includes an application processor (AP), the second semiconductor package includes a memory, and the third semiconductor package includes a power management integrated circuit (PMIC).

Abstract: A connection system of semiconductor packages includes: a printed circuit board having a first surface, and a second surface, opposing the first surface; a first semiconductor package disposed on the first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; and a second semiconductor package disposed on the second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures. The first semiconductor package includes an application processor (AP) and a power management integrated circuit (PMIC) disposed side by side, and the second semiconductor package includes a memory.

Abstract: An electronic component package includes: a frame, including a through-hole and a through-wiring; an electronic component disposed in the through-hole of the frame; a metal plate disposed on a first side of the electronic component and the frame; and a redistribution layer disposed on a second side of the electronic component opposing the first side and electrically connected to the electronic component.

Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface disposed to oppose the active surface; a dummy chip disposed in the through-hole and spaced apart from the semiconductor chip; a second connection member disposed on the first connection member, the dummy chip, and the active surface of the semiconductor chip; and an encapsulant encapsulating at least portions of the first connection member, the dummy chip, and the inactive surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads.

Abstract: An electronic component package includes: a frame, including a through-hole and a through-wiring; an electronic component disposed in the through-hole of the frame; a metal plate disposed on a first side of the electronic component and the frame; and a redistribution layer disposed on a second side of the electronic component opposing the first side and electrically connected to the electronic component.

Abstract: An actuator includes a magnet, a driving coil facing the magnet, a driver, and a position calculation processor. The driver is configured to move the magnet in at least one of an optical axis direction and a direction perpendicular to the optical axis by applying a driving signal to the driving coil. The position calculation processor includes sensing coils, and is configured to calculate a position of the magnet according to inductance levels of an inductor of the sensing coils. The inductance levels vary according to movements of the magnet.

Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface disposed to oppose the active surface; a dummy chip disposed in the through-hole and spaced apart from the semiconductor chip; a second connection member disposed on the first connection member, the dummy chip, and the active surface of the semiconductor chip; and an encapsulant encapsulating at least portions of the first connection member, the dummy chip, and the inactive surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads.

Abstract: An electronic component package includes: a frame, including a through-hole and a through-wiring; an electronic component disposed in the through-hole of the frame; a metal plate disposed on a first side of the electronic component and the frame; and a redistribution layer disposed on a second side of the electronic component opposing the first side and electrically connected to the electronic component.

Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface disposed to oppose the active surface; a dummy chip disposed in the through-hole and spaced apart from the semiconductor chip; a second connection member disposed on the first connection member, the dummy chip, and the active surface of the semiconductor chip; and an encapsulant encapsulating at least portions of the first connection member, the dummy chip, and the inactive surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads.

Abstract: An electronic component package includes: a lower package, including a frame including a through-hole and a through-wiring, a first electronic component disposed in the through-hole of the frame, a redistribution layer disposed below the first electronic component and the frame and electrically connected to the first electronic component, and an encapsulant filling the through-hole to encapsulate the first electronic component; an upper package disposed on the lower package and including a second electronic component; and a passive element disposed between the upper package and the lower package.

Abstract: An electronic component package includes: a frame, including a through-hole and a through-wiring; an electronic component disposed in the through-hole of the frame; a metal plate disposed on a first side of the electronic component and the frame; and a redistribution layer disposed on a second side of the electronic component opposing the first side and electrically connected to the electronic component.

Abstract: Provided is a liquid crystal display including: a first substrate; a gate line, a data line, and a common voltage line formed on the first substrate; a first passivation layer formed on the gate line, the data line, and the common voltage line; and a pixel electrode and a common electrode formed on the first passivation layer and overlapping each other with a second passivation layer therebetween, and the common electrode is connected to the common voltage line through a common contact hole, and the common contact hole is disposed for every two or more dots.

Abstract: An image sensor module is provided. The image sensor module includes a printed circuit board (PCB), an image sensor chip disposed on a first plane of the PCB and electrically connected to the PCB, and an image signal processing chip disposed on the first plane of the PCB and electrically connected to the PCB. An aspect ratio of the image signal processing chip is at least two times greater than an aspect ratio of the image sensor chip. A minimum feature size of a metal line implemented in the image sensor chip is at least 1.5 times greater than a minimum feature size of a metal line implemented in the image signal processing chip.

Abstract: Provided is a liquid crystal display including: a first substrate; a gate line, a data line, and a common voltage line formed on the first substrate; a first passivation layer formed on the gate line, the data line, and the common voltage line; and a pixel electrode and a common electrode formed on the first passivation layer and overlapping each other with a second passivation layer therebetween, and the common electrode is connected to the common voltage line through a common contact hole, and the common contact hole is disposed for every two or more dots.

Abstract: An image sensor module is provided. The image sensor module includes a printed circuit board (PCB), an image sensor chip disposed on a first plane of the PCB and electrically connected to the PCB, and an image signal processing chip disposed on the first plane of the PCB and electrically connected to the PCB. An aspect ratio of the image signal processing chip is at least two times greater than an aspect ratio of the image sensor chip. A minimum feature size of a metal line implemented in the image sensor chip is at least 1.5 times greater than a minimum feature size of a metal line implemented in the image signal processing chip.

Abstract: An image sensor, an image processing apparatus including the same and an interpolation method of the image processing apparatus are provided. The image sensor includes a plurality of pixels that include a low-luminance pixel including a first photoelectric conversion device that accumulates a charge less than a predetermined reference value and a high-luminance pixel including a second photoelectric conversion device that accumulates a charge more than the predetermined reference value. Interpolation is carried out giving more weight to the low-luminance pixel at low luminance and giving more weight to the high-luminance pixel at high luminance, so that a higher SNR is obtained.

Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

Abstract: Provided is a liquid crystal display including: a first substrate; a gate line, a data line, and a common voltage line formed on the first substrate; a first passivation layer formed on the gate line, the data line, and the common voltage line; and a pixel electrode and a common electrode formed on the first passivation layer and overlapping each other with a second passivation layer therebetween, and the common electrode is connected to the common voltage line through a common contact hole, and the common contact hole is disposed for every two or more dots.