Abstract: An apparatus controls a backlight of a display panel of a camera system. The apparatus includes a sub-pixel extracting unit, an ambient light luminance calculating unit, and a backlight controller. The sub-pixel extracting unit extracts sub-pixel luminance values from image data, where the image data is indicative of a current image frame defined by a plurality of pixels, and where each of the pixels includes a plurality of sub-pixels. The ambient light luminance calculating unit calculates an ambient light luminance value of the current image frame from the sub-pixel luminance values extracted by the sub-pixel extracting unit. The backlight controller which generates a backlight control signal based on a comparison between the calculated ambient light luminance value of the current image frame and an ambient light luminance value of a previous image frame.

Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

Abstract: An image sensor, an image processing apparatus including the same and an interpolation method of the image processing apparatus are provided. The image sensor includes a plurality of pixels that include a low-luminance pixel including a first photoelectric conversion device that accumulates a charge less than a predetermined reference value and a high-luminance pixel including a second photoelectric conversion device that accumulates a charge more than the predetermined reference value. Interpolation is carried out giving more weight to the low-luminance pixel at low luminance and giving more weight to the high-luminance pixel at high luminance, so that a higher SNR is obtained.

Abstract: An electronic information system comprises an external storage device and an application processor. The external storage device stores boot code and the application processor is adapted to receive the boot code from the external storage device and to perform a system booting operation during a power-up operation by executing the boot code.

Abstract: A booting method of a digital processing having a first processor and a second processor is provided. An interface between the first processor and the outside is stopped. A second processor program code is transmitted to a second memory from a first memory. A second stage loader (SSL) for the first processor is transmitted to a buffer of the second processor from the first memory. A first processor program code is transmitted to the second memory from the first memory under the control of the second processor and an interface between the first processor and the outside is resumed. The first processor program code is downloaded fast into the second memory to decrease booting time of the digital processing system.

Abstract: A flash memory system includes a flash memory for storing input data, and a memory controller controlling the flash memory, wherein the memory controller generates a first error correction code corresponding to the input data, and encrypts the first error correction code, and the flash memory includes a main area for storing the input data and a spare area for storing the encrypted first error correction code.

Abstract: An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2) comprises a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device.

Abstract: An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2) comprises a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device.

Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

Abstract: An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2) comprises a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device.

Abstract: A multi-level cell (MLC) memory device may include: a MLC memory cell; an outer encoder that encodes data using a first encoding scheme to generate an outer encoded bit stream; and a trellis coded modulation (TCM) modulator that applies a program pulse to the MLC memory cell to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream. A method of storing data in a MLC memory device, reading data from the MLC memory device, or storing data in and reading data from the MLC memory device may include: encoding data using a first encoding scheme to generate an outer encoded bit stream; and applying a program pulse to a MLC memory cell of the MLC memory device to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream.

Abstract: An image sensor module is provided. The image sensor module includes a printed circuit board (PCB), an image sensor chip disposed on a first plane of the PCB and electrically connected to the PCB, and an image signal processing chip disposed on the first plane of the PCB and electrically connected to the PCB. An aspect ratio of the image signal processing chip is at least two times greater than an aspect ratio of the image sensor chip. A minimum feature size of a metal line implemented in the image sensor chip is at least 1.5 times greater than a minimum feature size of a metal line implemented in the image signal processing chip.

Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

Abstract: An electronic information system comprises an external storage device and an application processor. The external storage device stores boot code and the application processor is adapted to receive the boot code from the external storage device and to perform a system booting operation during a power-up operation by executing the boot code.

Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

Abstract: An electronic information system comprises an external storage device and an application processor. The external storage device stores boot code and the application processor is adapted to receive the boot code from the external storage device and to perform a system booting operation during a power-up operation by executing the boot code.

Abstract: An apparatus controls a backlight of a display panel of a camera system. The apparatus includes a sub-pixel extracting unit, an ambient light luminance calculating unit, and a backlight controller. The sub-pixel extracting unit extracts sub-pixel luminance values from image data, where the image data is indicative of a current image frame defined by a plurality of pixels, and where each of the pixels includes a plurality of sub-pixels. The ambient light luminance calculating unit calculates an ambient light luminance value of the current image frame from the sub-pixel luminance values extracted by the sub-pixel extracting unit. The backlight controller which generates a backlight control signal based on a comparison between the calculated ambient light luminance value of the current image frame and an ambient light luminance value of a previous image frame.

Abstract: Provided are an apparatus and method of transmitting working context, which can minimize power consumption in a power-off standby mode of a portable apparatus including a system on a chip, where the method includes selecting a power-off standby mode, transmitting working context with respect to a hardware module, which is mounted on a semiconductor chip, to a predetermined memory, and storing the working context in the predetermined memory, transmitting the working context stored in the memory to a non-volatile memory outside the semiconductor chip, and storing the working context in the non-volatile memory, and executing the power-off standby mode; where the method may further include releasing the power-off standby mode, restoring the working context with respect to the hardware module, which is stored in the non-volatile memory, to the predetermined memory, and recovering the at least one hardware module to a state existing immediately before the power-off standby mode was executed by using the working con

Abstract: A processor system power voltage has low idle level as compared to a normal level during an idle mode. Power consumption of the processor during the idle mode is reduced. A power voltage supplied to the processor is increased to a normal level in returning to a normal mode from the idle mode, and a frequency of a clock signal supplied to the processor is decreased in comparison with a normal frequency. As a result, it is possible to prevent misoperation of the processor.

Abstract: A booting method of a digital processing having a first processor and a second processor is provided. An interface between the first processor and the outside is stopped. A second processor program code is transmitted to a second memory from a first memory. A second stage loader (SSL) for the first processor is transmitted to a buffer of the second processor from the first memory. A first processor program code is transmitted to the second memory from the first memory under the control of the second processor and an interface between the first processor and the outside is resumed. The first processor program code is downloaded fast into the second memory to decrease booting time of the digital processing system.